Paired-Channel Stacked Memory Routing for Capacity and Bandwidth
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current computing systems face challenges in efficiently accessing large data sets due to limitations in memory capacity and speed, particularly in artificial neural networks that require rapid and efficient data access as the number of processors and data sizes grow exponentially.
Innovation Solution
A 3D-IC stacked memory device with a base die that buffers memory transactions and provides flexible channel routing, allowing for simultaneous or near-simultaneous access to multiple memory dies via external and internal channels, supported by multiplexers and command decoders, which enables expanded memory capacity without reducing efficiency or speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is increased to meet growing data set requirements, then the ability to store larger data sets is improved, but access speed and efficiency deteriorate
Solution Approach 1:
The memory system is divided into multiple independent memory channels (Channel A and Channel B) that can operate simultaneously. Each channel has dedicated command/address and data pathways to memory dies, allowing parallel access to different memory regions. This segmentation enables the system to maintain high access speeds while scaling capacity by adding more channels rather than expanding a single channel's capacity.
Solution Approach 2:
The patent transitions from two-dimensional planar memory expansion to three-dimensional stacked memory architecture with vertical channels. Multiple memory dies are stacked vertically and accessed through vertical interconnects, adding a vertical dimension to memory expansion. This allows capacity scaling without proportionally increasing the footprint area and maintains access efficiency through direct vertical pathways.
2Productivity
If the number of processors is increased to enhance computing power, then processing capability is improved, but the complexity of data access coordination worsens
Solution Approach 1:
The base die incorporates a universal channel interface that can route commands and data to any memory channel through a shared command/address bus. The multiplexer system provides multi-functional routing capability, allowing a single command interface to service multiple memory channels sequentially or in parallel, reducing the need for separate dedicated interfaces for each channel and simplifying the overall system architecture.
Solution Approach 2:
The base die acts as an intermediary layer between the processor and the stacked memory dies. It contains command decoders, multiplexers, and routing logic that mediate between processor requests and the physical memory channels. This intermediary abstracts the complexity of multi-channel coordination from the processor, providing a simplified interface while managing the complexity of accessing multiple memory dies through vertical channels.
Data Source
AI summary
A stacked memory device includes memory dies over a base die. The base die includes separate memory channels to the different dies and external channels that allow an external processor access to the memory channels. The base die allows the external processor to access multiple memory channels using more than one external channel. The base die also allows the external processor to communicate through the memory device via the external channels, bypassing the memory channels internal to the device. This bypass functionality allows the external processor to connect to additional stacked memory devices.