Paired Core Architecture with Reversed Clock Phases for Memory Conflict Resolution
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Solution Overview
Problem
Multicore processors face issues with data coherency and interrupt response latency due to conflicts in accessing shared internal memory, with existing solutions either throttling performance through arbitration logic or increasing power consumption with dedicated caches.
Innovation Solution
A paired-core architecture where cores operate at reversed clock phases, allowing independent and conflict-free access to shared internal memory, eliminating the need for arbitration and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If arbitration logic is used to manage shared memory access in multicore processors, then data coherency is maintained, but performance is throttled due to access conflicts
Solution Approach 1:
The processor is divided into paired cores (first core and second core) that operate independently with exclusive access to shared internal memory at different clock phases, eliminating arbitration needs and maintaining both data coherency and high performance
Solution Approach 2:
The paired cores operate at reversed clock phases, creating a periodic pattern where one core accesses memory during its phase while the other core is inactive, ensuring exclusive access without conflicts and maintaining data coherency naturally
2Productivity
If dedicated caches are provided for each core to eliminate access conflicts, then processor performance is improved, but power consumption increases
Solution Approach 1:
Multiple cores share a single internal memory resource instead of each core having a dedicated cache, reducing overall memory capacity requirements and power consumption while paired-core phasing ensures conflict-free access maintaining performance
Solution Approach 2:
Cores access shared memory in alternating periodic phases, ensuring exclusive access during each phase without requiring dedicated caches, thus maintaining high performance while reducing power consumption through shared memory resources
3Adaptability or versatility
If multiple microcontrollers are used to control different hardware blocks in real time, then system functionality is improved, but device complexity increases
Solution Approach 1:
Multiple cores within a single multicore processor perform the functions previously requiring separate microcontrollers, enabling real-time control of multiple hardware blocks while reducing overall device complexity through integration
Solution Approach 2:
Multiple processing units are merged into a single multicore processor package with shared resources, reducing the total number of discrete microcontrollers needed while maintaining the ability to control multiple hardware blocks in real time
Data Source
AI summary
An architecture in which the cores of a multicore processor are paired together. An internal memory may be connected to the pair of cores via separate leads. The pair of cores can run at reversed clock phases. A clock generator may be responsible for generating a clock signal that can be provided as input to one core, and a signal inverter may be responsible for inverting the clock signal so as to generate an inverted clock signal that can be provided as input to the other core.