Dual Shift Register Scan Control for LCD Gate Driver Delay
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Solution Overview
Problem
Large LCD devices face image quality deterioration due to increased propagation delay of gate driving voltage in lengthened gate lines and the challenge of accommodating a gate driver within limited design areas, especially as LCDs grow in size.
Innovation Solution
A dual shift register design that includes two sets of stages with scan direction controllers and output portions, using multiple clock signals with sequential and circular phases to generate and distribute scan pulses, allowing for reduced area occupation and stable voltage application across gate lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the gate driver is mounted on the LCD panel, then the gate driver can be integrated with the display, but the gate driver occupies a relatively large area
Solution Approach 1:
The gate driver is divided into multiple shift registers (first shift register and second shift register) that are distributed across different regions of the LCD panel. Each shift register handles a portion of the gate lines, allowing the gate driving function to be segmented and distributed rather than concentrated in a single large block, thus reducing the area occupied by the gate driver while maintaining integration.
2Area of stationary object
If the LCD device is enlarged in size, then the display area increases, but the propagation delay of the gate driving voltage increases
Solution Approach 1:
The gate driver function is segmented into multiple shift registers distributed across the LCD panel. This segmentation reduces the distance that scan pulses must travel within each shift register, thereby reducing the propagation delay of the gate driving voltage even as the overall display area increases.
Solution Approach 2:
Instead of concentrating the gate driver in a single location, the shift registers are distributed in a two-dimensional arrangement across the LCD panel. This spatial distribution in multiple dimensions reduces the maximum distance any scan pulse must travel, effectively reducing propagation delay while accommodating larger display areas.
3Device complexity
If a single shift register is used, then the structure is simple, but the gate driver occupies a large area and causes propagation delay
Solution Approach 1:
The single shift register is segmented into multiple shift registers (first and second shift registers) with paired stages. While this increases structural complexity, it dramatically reduces the area occupied by each individual shift register and reduces propagation delay by distributing the scanning function across multiple units.
Data Source
AI summary
Disclosed is a dual shift register that includes a first shift register configured to include a plurality of stages which sequentially output scan pulses using at least two clock signals with sequential and circular phases, and a second shift register configured to a plurality of stages which form pair with the respective stages of the first shift register and sequentially output the scan pulses using at least two clock signals. Each stage includes: a scan direction controller configured to respond to the scan pulses from previous and next stages and to selectively output forward and reverse direction voltages with opposite electric potentials to each other; and an output portion configured to respond to the output signal of the scan direction controller, to generate two sequential scan pulses using two of the at least two clock signals, and to distribute the sequential scan pulses to the previous and next stages.