Selective Palladium Diffusion for Buried p-Layer Formation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for manufacturing power semiconductor devices with selectively processed p-layers are complex and not easily applicable to devices requiring localized avalanche ruggedness, such as chip diodes with planar junction termination, where a continuous Palladium layer is not desired.
Innovation Solution
A method involving the creation of a surface layer of Palladium particles on a wafer, followed by ion irradiation and diffusion at temperatures not exceeding 750 °C, allowing for the formation of buried p-doped layers with controlled carrier lifetime in specific areas, using a masking process to ensure precise placement of the p-layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a continuous Palladium layer is introduced into the diode by radiation enhanced diffusion, then the breakdown voltage of the device is improved and dynamic avalanche is postponed to higher voltages, but such a layer is applied over the whole plane which is not desired in chip diodes with planar junction termination
Solution Approach 1:
The patent applies local quality by creating selective Palladium layers only in specific regions of the semiconductor device through a multi-step process: first forming a continuous Palladium layer, then selectively removing it in certain areas using etching or lift-off techniques, and finally performing ion irradiation and thermal treatment only in the desired regions. This allows the device to have different properties in different areas - with Palladium layers for avalanche ruggedness where needed and without them in termination regions.
2Reliability
If complex processing methods are used to create p-type columns in compensation type devices, then the spatial distribution of the electric field can be flattened, but the processing becomes rather complex with several steps
Solution Approach 1:
The patent merges multiple processing functions into a single integrated process. Instead of using separate steps for creating p-type columns, forming masks, and performing ion implantation, the invention combines these operations by using the Palladium layer itself as both the mask material and the diffusing species. The Palladium layer is selectively removed in desired patterns, and then ion irradiation followed by thermal treatment simultaneously creates the p-type regions and controls the electric field distribution, reducing the total number of processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the creation of semiconductor devices with buried p-layers that enhance avalanche ruggedness while maintaining low leakage current, offering improved thermal stability and simplifying the manufacturing process by reducing the number of processing steps and avoiding the limitations of standard diffusion methods.
Implementation Method 1
the wafer is irradiated on the first main side with ions
Implementation Method 2
a homogeneous, continuous layer with Palladium and Palladium related defects is introduced into the diode by radiation enhanced diffusion (RED)
Implementation Method 3
afterwards the palladium particles are diffused (41) into the wafer at a temperature of not more than 750 °C
Implementation Method 4
the anode side is irradiated with alpha particles giving a defect peak in a depth of about 70 μm
Data Source
Figure 1A~3B
Figure 4A~6B
Figure 7A~11
AI summary
A method for manufacturing a power semiconductor device, which comprises a first electrical contact (2) on a first main side (21) and a second electrical contact (3) on a second main side (31) opposite the first main side (21) and at least a two-layer structure with layers of different conductivity types, comprises at least the following manufacturing steps: an n doped wafer (1) is provided, a surface layer (4, 4', 4", 4'") of palladium particles is created on the first main side (21), the wafer (1) is irradiated (5) on the first main side (21) with ions, afterwards the palladium particles are diffused (41) into the wafer at a temperature of not more than 750 °C, by which diffusion a first p doped layer (7) is created, afterwards the first and second electrical contacts (2, 3) are created, characterized in that at least the step of the irradiation (5) with ions is performed through a mask (45).