PAM-2N Data Encoding for Stable Clock Data Recovery

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Solution Overview

Problem

Existing PAM-4 systems face challenges with clock data recovery due to DC imbalance in data transmission, leading to inefficient clock generation and reduced data modulation accuracy.

Innovation Solution

A PAM-2N system with a data encoder that alternately aligns MSBs and LSBs, generates encoded de-serialized data, and uses a CDR to improve DC balance, enabling optimized clock data recovery.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If CDR technology is used to reduce the number of clock lanes, then the number of pins in a package is reduced, but the frequency of the clock CLK becomes different from the transfer rate of received data when data information is not updated

Engineering Contradiction:

Improvenumber of clock lanesVSAvoidfrequency matching between clock and data

Core Design Contradiction:

Device complexityVSMeasurement precision

Solution Approach 1:

The system applies 8B/10B encoding to data before transmission to ensure DC balance is maintained in advance. This preliminary encoding ensures that even when data values remain constant for extended periods, the encoded representation maintains sufficient transitions to allow the CDR circuit to accurately track and regenerate the clock signal at the correct frequency.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary encoding layer (8B/10B encoder) between the data source and the CDR circuit. This encoder transforms the original data into a DC-balanced format that serves as a mediator, ensuring that the CDR receives data with sufficient transitions to maintain accurate frequency synchronization without requiring additional clock lanes.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Measurement precision

If 8B/10B encoding is adopted to generate DC-balanced data, then clock frequency synchronization is improved, but the system complexity increases

Engineering Contradiction:

Improveclock frequency synchronizationVSAvoidencoding complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The system changes the parameter representation of data from raw binary values to 8B/10B encoded values with controlled DC balance. By transforming the data parameter structure, the system achieves better clock synchronization characteristics without requiring fundamental changes to the CDR architecture or adding complex external synchronization circuits.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If data are transmitted at higher speed to increase data rate, then transmission efficiency is improved, but the bandwidth of signal is doubled when two bit streams are serialized

Engineering Contradiction:

Improvedata rateVSAvoidsignal bandwidth

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The 8B/10B encoding scheme introduces a periodic structure to the data stream by ensuring DC balance over fixed 10-bit intervals. This periodicity creates regular transitions that aid clock recovery while maintaining the same signal bandwidth, allowing high data rates to be achieved without proportionally increasing bandwidth requirements through techniques like simple serialization.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS20250385778A1PAM-2n system having optimized clock data recovery characteristic

Publication Date: 2025.12.18 KUMOH NAT INST OF TECH IND ACADEMIC COOPERATION FOUND

AI summary

Proposed is a PAM-2N system which can support a training pattern and has an optimized clock data recovery characteristic through data encoding. The PAM-2N system having an optimized clock data recovery characteristic includes a receiver, a de-serializer, a data encoder, a PAM-2N transmitter, a PAM-2N receiver, a CDR, and a serializer & transmitter.