PAM Decoder Architecture With 1+D Pulse Shaping and Split ADCs
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Solution Overview
Problem
Mid-reach backplane wireline communication systems face significant channel loss and require extensive equalization and clock/data recovery to achieve low bit error rates, necessitating improved receiver performance and reduced power consumption.
Innovation Solution
A decoder system comprising a signal amplifier, demultiplexer, and multiple ADCs, along with a receiver that includes a phase interpolator and processor, to enhance performance and reduce power consumption by utilizing 1+D pulse shaping and adaptive calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If extensive equalization techniques are performed to compensate for channel loss, then bit error rate is reduced, but device complexity and power consumption increase
Solution Approach 1:
The receiver is divided into multiple independent decoders (first decoder, second decoder, third decoder, fourth decoder), each handling a portion of the data signal. This segmentation reduces the complexity burden on any single decoder while maintaining overall system reliability through parallel processing of equalization tasks.
Solution Approach 2:
Each decoder performs a subset of the total equalization function with optimized parameters tailored to its specific processing stage. The first decoder handles initial equalization, while subsequent decoders perform refined equalization, distributing the overall complex task into manageable partial actions that reduce individual complexity.
2Reliability
If clock and data recovery circuitry is added to properly sample and decode data, then bit error rate is reduced, but power consumption increases
Solution Approach 1:
The clock and data recovery function is segmented across multiple decoders, each with its own phase interpolator and deskewer circuitry. This allows parallel recovery operations that distribute power consumption across multiple lower-power units rather than requiring a single high-power recovery system.
Solution Approach 2:
The phase interpolators generate multiple interpolated clock signals at different phases, which are then processed through periodic deskewing operations. This periodic phase adjustment mechanism enables efficient clock recovery with reduced power consumption by utilizing periodic rather than continuous high-power operations.
3Measurement precision
If multiple ADCs with different bit depths are used for decoding, then decoding accuracy is improved, but device complexity increases
Solution Approach 1:
The ADCs are divided into two functional groups: first ADCs with (M+2) bits for capturing fine-grained signal details and error information, and second ADCs with (M+1) bits for standard decoding. This segmentation allows each ADC type to be optimized for its specific function, improving overall accuracy while managing complexity through standardized component families.
Solution Approach 2:
Different ADCs are assigned different bit depths based on their specific functional requirements within the decoding system. The first ADCs receive higher bit depth locally where maximum precision is needed for error detection, while second ADCs use appropriate bit depth for their decoding function, optimizing the accuracy-complexity tradeoff at each local position.
Data Source
AI summary
A decoder includes a signal amplifier, a demultiplexer and multiple ADCs. The signal amplifier receives a to-be-amplified data signal that originated from an input data signal in a PAM-2M format and that is in a PAM-(2M+1−1) format because of 1+D pulse shaping, and performs amplification and level shifting on the to-be-amplified data signal to generate a to-be-decoded data signal, where M≥2. The demultiplexer receives the to-be-decoded data signal, and demultiplexes the to-be-decoded data signal into multiple demultiplexed data signals to be respectively received by the ADCs. One of the ADCs is an (M+2)-bit ADC, and converts the corresponding demultiplexed data signal into a first decoded signal containing an (M+1)-bits wide data portion and a one-bit wide error portion. Each of the other one(s) of the ADCs is an (M+1)-bit ADC, and converts the corresponding demultiplexed data signal into a second decoded signal containing an (M+1)-bits wide data portion.