PAM Driver Multiplexer Layout to Eliminate Mid-Level DC Current
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Solution Overview
Problem
Pulse Amplitude Modulation (PAM) communication methods, such as PAM-4, often result in inherent direct current (DC) in mid-level states, which limits their use in electrical circuits with multiple channels and slower transmission interfaces, and are power-intensive, making it challenging to increase bandwidth without increasing power consumption.
Innovation Solution
The semiconductor device employs a '1-hot' analog multiplexer with high-speed buffers and reference voltages to eliminate DC current in mid-level states by configuring MOSFETs as a multiplexer, allowing only one path for output and using pre-positioning circuits to adjust voltages during state transitions, reducing power consumption and increasing bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If PAM-4 communication method is used, then bandwidth is increased, but DC current is generated in mid-level states
Solution Approach 1:
The output driver is segmented into multiple independent push-pull output drivers, each capable of driving to different voltage levels. This segmentation allows selective activation of individual drivers to achieve intermediate voltage states without generating DC current, as each driver independently switches between voltage levels rather than maintaining a continuous DC component.
Solution Approach 2:
The system dynamically transitions between different output voltage levels (0V, 0.5V, 1.0V, 1.5V, 2.0V) based on the data being transmitted. By dynamically switching between discrete voltage levels rather than maintaining fixed intermediate levels, the system achieves PAM-4 modulation without creating inherent DC current in mid-level states.
2Productivity
If PAM-4 communication method is used, then bandwidth is increased, but power consumption increases
Solution Approach 1:
The system uses partial action by selectively activating only the necessary number of push-pull output drivers based on the current voltage level requirement. Instead of continuously driving all drivers at full power, the system activates only the minimal number of drivers needed to achieve the desired voltage level, thereby reducing overall power consumption while maintaining high bandwidth capability.
Solution Approach 2:
The system changes the voltage level parameter dynamically across five discrete levels (0V, 0.5V, 1.0V, 1.5V, 2.0V) to encode data. By using variable voltage levels rather than fixed levels, the system achieves higher bandwidth through more states per signal while controlling power consumption through selective driver activation at each voltage level.
3Productivity
If multiple channels are used, then bandwidth is increased, but DC current interference increases
Solution Approach 1:
Each channel is equipped with independent push-pull output drivers that can be controlled separately. This segmentation allows each channel to independently manage its voltage levels and switching operations, preventing DC current from one channel from interfering with adjacent channels. The independent control ensures that intermediate voltage states are achieved through dynamic switching rather than DC coupling between channels.
4Device complexity
If conventional PAM driver is used, then simplicity is maintained, but DC current cannot be eliminated
Solution Approach 1:
The patent merges multiple push-pull output driver circuits into a single integrated output stage that can collectively produce multiple voltage levels. By combining the functionality of multiple drivers under unified control, the system achieves the ability to eliminate DC current in mid-level states while maintaining a relatively simple integrated structure rather than requiring completely separate driver circuits for each function.
Data Source
AI summary
Devices and methods are described herein for a pulse amplitude modulation (PAM) driver. In one embodiment, the PAM driver includes a first high-speed buffer configured to output a first voltage, a second high-speed buffer configured to output a second voltage, and a plurality of transistors coupled to the first high-speed buffer and the second high-speed buffer. At least one of the first voltage or the second voltage facilitates selective operation of a transistor of the plurality of transistors to output a third voltage.