Two-Layer PAM Phase Detection for Lower Front-End Load

The patent segments the decoding process into two distinct layers: a first-layer comparator structure that performs initial signal comparison and generates error information, and a second-layer comparator structure that processes reset speeds to generate data information. This segmentation reduces the hardware burden on the front-end circuit by distributing processing tasks across multiple specialized stages, thereby maintaining high data transfer rates while reducing overall hardware complexity and power consumption.

The patent introduces an intermediary least mean square (LMS) engine that acts as a mediator between the comparator structures and the decision-making process. The LMS engine processes error information from the first-layer comparators and adjusts critical voltages dynamically, enabling accurate frequency tracking and noise tolerance with reduced phase detection density. This intermediary processing allows the system to maintain reliability while operating with lower hardware burden and power consumption.

The patent transitions from a single-layer decoding approach to a two-layer comparator structure with vertical dimensionality. The first-layer comparators operate in parallel to generate error information, while the second-layer comparators process reset speeds in a subsequent dimension. This dimensional restructuring allows extensive decoding capability to be achieved without concentrating all processing load in the front-end circuit, thereby preserving system bandwidth while maintaining high data transfer rates.