PAM Receiver DFE Circuit with Candidate Selection for Lower Chain Delay
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Solution Overview
Problem
Existing digital processing circuits face time constraints due to the accumulation of delay in the chain path of decision feedback equalizer (DFE) circuits, which are used to compensate for signal loss from inter-symbol interference (ISI), particularly in high-speed data transmission systems.
Innovation Solution
A digital processing circuit is designed with a DFE circuit that includes a candidate generation circuit to probabilistically resolve delay accumulation by generating candidate signals based on weighted coefficients and a chain multiplexer circuit to select the correct symbol value, utilizing a 2:1 multiplexer structure to reduce intrinsic delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a chain path structure is used in DFE circuits to determine symbol values sequentially, then the equalization function is achieved, but delay accumulates in the chain path causing time constraints
Solution Approach 1:
The patent segments the chain path delay problem by introducing two distinct processing paths: a first path for determining previous symbol values and a second path for determining present symbol values. This segmentation allows parallel processing of different symbol determination operations, preventing delay accumulation in a single sequential chain path while maintaining the necessary equalization accuracy.
2Productivity
If multiple multiplexer circuits operate in parallel, then processing speed increases, but delay accumulation occurs in the chain path
Solution Approach 1:
The patent resolves the delay accumulation by transitioning from a single-dimensional sequential chain path to a two-dimensional processing structure with multiple independent paths. The first path handles previous symbol determination while the second path handles present symbol determination, allowing parallel operation without delay accumulation in a single chain.
3Loss of time
If the chain path is simplified to reduce delay, then time constraints are met, but the equalization performance may be compromised
Solution Approach 1:
The patent introduces an intermediary structure in the form of a second multiplexer circuit that selectively determines present symbol values based on received data. This intermediary allows the system to bypass unnecessary sequential delays while maintaining accurate equalization by selecting appropriate calculation results based on the actual input data conditions.
Data Source
AI summary
A digital processing circuit includes a first feed forward equalizer (FFE) circuit configured to equalize a digital signal including a plurality of symbols according to a pulse amplitude modulation (PAM) method and to output a first equalization signal; a second FFE circuit configured to equalize the digital signal and to output a second equalization signal; and a decision feedback equalization (DFE) circuit. The DFE circuit generates a plurality of candidate values using: i) a first equalization signal of a first region associated with a previous symbol, ii) a second region associated with the present symbol and iii) the present symbol. The DFE circuit inputs the symbol value of the previous symbol as a select signal, and selects one of the plurality of candidate values and outputs the value as a symbol value of the present symbol.