PAM Receiver Slicer Feedback for Faster ISI Decoding
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Solution Overview
Problem
High-speed communication receivers face challenges in accurately decoding pulse amplitude modulated (PAM) signals due to inter-symbol interference (ISI), which leads to distortion and requires complex circuitries that degrade performance and consume additional resources.
Innovation Solution
The system employs a set of slicers, a speculative tap, a decoder, and a feedback generator to select bits based on prior slicer output signals, reducing critical path delay and mitigating ISI through clock kickback compensation and feedback loops, thereby improving operating speed and sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If complex circuitries are used to compensate for ISI distortion, then decoding accuracy is improved, but receiver speed and hardware resources are degraded
Solution Approach 1:
The receiver is divided into multiple independent slicers, each responsible for detecting a specific voltage level. This segmentation allows parallel processing of different signal levels without requiring complex sequential circuitries, thereby maintaining high decoding accuracy while preserving receiver speed.
Solution Approach 2:
The slicers perform preliminary amplitude detection and level classification before the decoding stage. By pre-processing the signal amplitude information in parallel through multiple slicers, the system eliminates the need for complex distortion compensation circuitries during the main decoding process, thus maintaining both accuracy and speed.
2Measurement precision
If complex circuitries are used to compensate for ISI distortion, then decoding accuracy is improved, but hardware resources are consumed
Solution Approach 1:
The receiver architecture is segmented into multiple independent slicers that operate in parallel, each handling a specific voltage level detection. This eliminates the need for complex sequential distortion compensation circuitries, reducing hardware resources while maintaining decoding accuracy through distributed parallel processing.
Solution Approach 2:
Each slicer is designed to autonomously detect and classify signal levels based on predefined voltage thresholds. This self-service capability of individual slicers eliminates the need for additional complex compensation circuitries, reducing overall hardware complexity while maintaining accurate decoding through the collective operation of multiple simple, independent units.
Data Source
AI summary
Disclosed herein are related to a system and a method for high speed communication. In one aspect, the system includes a set of slicers configured to generate a slicer output signal digitally indicating a level of an input signal received by the set of slicers. The system includes a speculative tap coupled to the set of slicers, where the speculative tap is configured to select bits of the slicer output signal based on selected bits of a prior slicer output signal. The system includes a decoder coupled to the speculative tap, where the decoder is configured to decode the selected bits of the slicer output signal in a first digital representation into a second digital representation. The system includes a feedback generator coupled to the decoder, where the feedback generator is configured to generate a feedback signal according to the decoded bits of the slicer output signal.