PAM Receiver Reference Slicing Without a High-Speed ADC
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Solution Overview
Problem
High-speed data links using multi-level amplitude signaling face increased transceiver complexity and power consumption due to the need for high-speed analog-to-digital converters, which are costly and power-intensive.
Innovation Solution
A receiver circuit architecture that includes a peak detector and a reference voltage generator to automatically align slicing voltage levels, reducing the number of required samplers and eliminating the need for a front-end ADC, using a comparator circuit to detect amplitude levels in multi-level amplitude signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If PAM signaling is implemented to increase data rate, then effective data rate is improved, but transceiver complexity increases
Solution Approach 1:
The patent changes the parameter of voltage level quantization by using a peak detector to dynamically determine the maximum voltage level and then generating multiple reference voltages based on this peak value. This allows the system to adapt to different signal amplitudes and reduces the need for fixed, high-precision ADC circuits, thereby maintaining high data rates while reducing transceiver complexity
Solution Approach 2:
Instead of using a complex high-speed ADC to directly digitize the PAM signal, the patent creates simplified copies of the signal through multiple comparators that each compare the input signal against a specific reference voltage. These comparator outputs collectively represent the digitized signal without requiring a single complex ADC circuit, thus reducing complexity while maintaining functionality
2Measurement precision
If high-speed ADC circuit is implemented to digitize PAM signal, then signal digitization is achieved, but power consumption increases
Solution Approach 1:
The patent segments the single high-power ADC operation into multiple lower-power comparator operations. Each comparator operates independently at lower speed and lower power consumption, comparing the signal against a specific reference voltage level. The collective output of these segmented comparators achieves the same digitization function as a single high-speed ADC would provide, but with significantly reduced power consumption
Solution Approach 2:
The patent replaces the expensive, power-intensive high-speed ADC with multiple simpler, lower-cost comparator circuits. These comparators are functionally sufficient for the application and can be implemented with simpler circuitry that consumes less power, effectively using 'cheaper' components to achieve the required functionality without the overhead of a high-performance ADC
3Measurement precision
If high-speed ADC circuit is implemented to digitize PAM signal, then signal digitization is achieved, but circuit area increases
Solution Approach 1:
The patent divides the single large ADC circuit into multiple smaller comparator circuits distributed across the chip. Each comparator occupies a smaller area and performs a specific comparison function. The modular nature of these segmented comparators allows for more efficient space utilization compared to a single monolithic ADC circuit, reducing the total circuit area while maintaining digitization accuracy
Solution Approach 2:
Instead of implementing a single complex ADC circuit that occupies large area, the patent creates multiple simplified comparator copies that together perform the digitization function. These comparator copies are much smaller in area individually and collectively require less total chip real estate than a high-speed ADC would require, thus reducing circuit area while achieving the same functional outcome
Data Source
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AI summary
One aspect relates to a receiver circuit for multi-level amplitude signaling which includes at least three amplitude levels for each symbol period. The receiver circuit (200) includes a peak detector (204), a reference voltage generator (206), and a comparator circuit (208). The peak detector (204) is arranged to detect a peak voltage of the multi-level amplitude signal, and the reference voltage generator (206) uses the peak voltage to generate multiple reference voltages. The comparator circuit (208) uses the multiple reference voltages to detect an amplitude level of the multi-level amplitude signal. Other aspects and features are also disclosed.