Baud-Rate PAM Timing Recovery Using Adaptive Interpolation
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Solution Overview
Problem
Existing digital communication receivers face challenges in timing recovery at baud-rate sampling rates, as standard interpolation techniques are impractical below the Nyquist rate, leading to high costs and complexity in clock control for fast data communication standards like Gigabit Ethernet.
Innovation Solution
A method employing an adaptive linear filter for baud-rate interpolation, utilizing the structure of PAM signals and smooth channel pulse responses, with LMS algorithm adaptation, to reduce the number of clock phases required for A/D clock control, allowing for simple and inexpensive control of the analog clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard interpolation techniques are used for timing recovery at baud-rate sampling, then timing recovery can be performed, but the technique is impractical because the sampling rate is below the Nyquist rate
Solution Approach 1:
The patent changes the sampling rate parameter from high-rate (above Nyquist) to baud-rate (below Nyquist) and develops interpolation techniques specifically adapted to this parameter regime. The invention modifies the interpolation approach to work with one sample per symbol, making timing recovery practical at baud-rate sampling by changing the fundamental sampling rate parameter.
Solution Approach 2:
The patent replaces the need for expensive voltage-controlled oscillators (VCO) that directly control the A/D clock with a digital interpolation system. This substitution uses digital signal processing to achieve timing recovery, replacing the mechanical/electrical VCO system with a digital computation-based system that is more suitable for integrated circuits.
2Reliability
If a voltage controlled oscillator is used to modify the A/D clock signal for timing recovery, then timing recovery is achieved, but the solution is expensive and complex
Solution Approach 1:
The patent replaces the voltage-controlled oscillator (VCO) system with a digital interpolation system. Instead of using an analog VCO to modify the A/D clock signal, the invention uses digital filtering and interpolation of the A/D output samples to achieve timing recovery. This substitution eliminates the need for expensive and complex analog clock control circuits.
Solution Approach 2:
The patent creates a digital copy of the timing adjustment function that was previously performed by the VCO. Rather than modifying the actual clock signal in the analog domain, the invention performs timing recovery by digitally interpolating between samples, effectively copying the timing adjustment function into the digital domain where it can be implemented with simpler, more integrated circuitry.
3Device complexity
If the A/D converter samples with a free-running clock and digital interpolation is used, then the clock control is simpler, but standard interpolation is impractical at baud-rate sampling below the Nyquist rate
Solution Approach 1:
The patent changes the sampling rate parameter to baud-rate (one sample per symbol, below Nyquist) and develops interpolation techniques specifically adapted to this parameter regime. The invention modifies the interpolation approach to work with this specific sampling rate, making it applicable to fast digital data communication standards like Gigabit Ethernet that require baud-rate sampling.
Solution Approach 2:
The patent implements an adaptive interpolation system that can dynamically adjust to timing errors. The interpolator uses feedback from timing error detection to adjust its parameters, making the system versatile and adaptable to different timing conditions while maintaining simplicity in the clock control architecture.
Data Source
AI summary
A timing recovery method enables interpolation of PAM signals sampled at baud rate. The method exploits the structure of the PAM signal and also the smoothness of the channel pulse response. The resulting interpolator is an adaptive linear filter; and its taps can be adapted with the LMS algorithm. Using this interpolator enables a user to significantly reduce the complexity of the analog clock control circuit. A Gigabit Ethernet receiver that controls the A/D clock by selecting one of several evenly space clock phases, for example, reduced the required number of clock phases from 64 to 16.