PAM Transceiver Adaptive Filtering Without Multiplier Circuits
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Solution Overview
Problem
Existing transceiver circuits face inefficiencies in processing multiple PAM modulation levels due to the need for complex multiplier circuits, which occupy significant space and power, making it difficult to efficiently support a range of PAM modulation levels like PAM-2, PAM-3, and PAM-4 within a single hardware setup.
Innovation Solution
The transceiver circuit employs adaptive filtering with tap weighting blocks and coefficient adaption units that utilize integer scaling factors and avoid multipliers by using 3× slicer normalization, enabling efficient processing of PAM-2, PAM-3, and PAM-4 through the use of adders and shift operators instead of multipliers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiplier circuits are used to process multiple PAM modulation levels, then the transceiver can support PAM-2, PAM-3, and PAM-4, but the hardware complexity and power consumption increase significantly
Solution Approach 1:
The patent changes the parameter representation by using 3× normalization where PAM-4 symbols are scaled to {−3, −1, 1, 3} instead of the conventional {−1.5, −0.5, 0.5, 1.5}. This integer-based parameter transformation eliminates the need for complex multiplier circuits, as integer scaling can be achieved through simple addition operations. The coefficient adaptation unit adjusts coefficients based on these normalized integer values, enabling multi-level PAM support with reduced hardware complexity.
Solution Approach 2:
The patent substitutes the mechanical multiplier circuit with an adder-based system. Instead of using physical multiplication operations to handle different PAM modulation levels, the invention uses addition operations with scaled coefficients. The tap weighting blocks use adders to combine incoming symbols with adapted coefficients, replacing the need for multiplier circuits while maintaining the ability to process PAM-2, PAM-3, and PAM-4 signals.
2Adaptability or versatility
If multiplier circuits are used to process multiple PAM modulation levels, then the transceiver can support PAM-2, PAM-3, and PAM-4, but the power consumption increases
Solution Approach 1:
The parameter transformation to 3× normalized integer values {−3, −1, 1, 3} enables the use of addition-based coefficient adaptation instead of multiplication. This parameter change reduces power consumption because adder circuits consume significantly less power than multiplier circuits, especially when processing multiple PAM modulation levels dynamically.
Solution Approach 2:
The substitution of multiplier circuits with adder-based tap weighting blocks directly reduces power consumption. The coefficient adaptation unit uses addition operations to update coefficients based on error signals and normalized symbols, eliminating the high power consumption associated with continuous multiplication operations in multi-level PAM processing.
3Measurement precision
If complex multiplier circuits are used, then accurate coefficient adaptation for interference cancellation can be achieved, but the hardware space occupied increases
Solution Approach 1:
The 3× normalization transforms the coefficient adaptation problem into an integer-based system where accuracy is maintained through addition operations. The normalized symbols {−3, −1, 1, 3} allow for precise coefficient updates using adders, achieving the same adaptation accuracy as multipliers would provide, but with reduced hardware footprint.
Solution Approach 2:
The replacement of multiplier circuits with adder-based tap weighting blocks significantly reduces the hardware area occupied. Adder circuits are fundamentally smaller and more area-efficient than multiplier circuits, allowing the transceiver to maintain coefficient adaptation accuracy while occupying less silicon real estate.
Data Source
AI summary
A transceiver circuit for transmitting and receiving pulse amplitude modulation, PAM, network signals within a network, wherein the PAM network signals can take a value according to a PAM modulation level of any of two-level modulation, three-level modulation or four-level modulation. The transceiver circuit comprises: a receiver-input-terminal for receiving a network signal, an interference cancellation block and an adaptive filtering circuit. The adaptive filtering circuit comprises: a filter-input-terminal; a filter-output-terminal; and a plurality of tap weighting blocks. Each tap weighting block comprises: a tap-input-terminal, a coefficient-input-terminal and a multiplexer. The adaptive filtering circuit also comprises one or more tap summation blocks configured to combine the output of each tap weighting block to provide an interference-error signal to the filter-output-terminal. The interference cancellation block subtracts the interference-error signal from the network signal to provide the processed-network-signal.