PAM3 Chiplet Transceiver Using Clock Reference Against Noise Offset
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Solution Overview
Problem
Chiplets experience high noise and reference offset due to integrated digital chips, leading to increased bit error rates during high-speed single-ended signal transmission, which conventional methods struggle to address effectively.
Innovation Solution
Implementing a PAM3 multi-level signaling method with capacitive equalizers and differential clock signals to modulate and decode signals, reducing noise and reference offset by differential comparison.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If single-ended signals are transmitted at high speed in chiplet, then productivity is improved, but noise and reference offset increase leading to higher bit error rates
Solution Approach 1:
The patent introduces clock signals as an intermediary reference to mediate the comparison between transmitted and received signals. By using clock signals as a common reference point between transmitter and receiver, the system can perform differential comparison to eliminate noise and reference offset effects, thereby maintaining signal integrity at high transmission speeds
Solution Approach 2:
The patent changes the signaling method from conventional single-level signaling to PAM3 multi-level signaling. This parameter change allows encoding more data per symbol period, increasing transmission speed while the accompanying differential comparison technique maintains reliability by eliminating noise effects
2Productivity
If multiple digital chips are integrated in chiplet, then productivity is improved, but noise in supply voltage and ground node increases
Solution Approach 1:
The patent uses clock signals as an intermediary reference that is distributed to both transmitter and receiver. This common reference allows the system to perform differential comparison that cancels out noise from supply voltage and ground nodes, enabling high integration density without compromising signal quality
Solution Approach 2:
The patent establishes a common reference potential through the distribution of clock signals across the chiplet. By ensuring both transmitter and receiver use the same clock reference, the system creates equipotential conditions that eliminate reference offset caused by noise in power and ground networks
3Device complexity
If single-ended signal transmission is used, then device complexity is reduced, but noise susceptibility increases
Solution Approach 1:
The patent introduces clock signals as a mediator that enables noise cancellation in single-ended transmission. By comparing the received signal against the received clock signal, the system can eliminate noise effects while maintaining the simplicity of single-ended transmission architecture
Solution Approach 2:
The patent replaces complex differential signaling hardware with a simpler single-ended transmission system that uses temporal comparison against clock signals. This substitution maintains noise immunity through signal processing rather than through hardware complexity
Data Source
AI summary
A semiconductor package according to an embodiment of the present disclosure includes a chiplet including a first die and a second die, a transmission chip included in the first die, configured to modulate single-ended data into a PAM3 multi-level signal, and configured to transmit the PAM3 multi-level signal and a plurality of clock signals to the second die, and a reception chip included in the second die and configured to generate single-ended data by differentially comparing the PAM3 multi-level signal with the plurality of clock signals received from the first die. The transmission chip are connected to the reception chip through a plurality of channels.