Clock Recovery Circuit for PAM3 Signal Conversion
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Solution Overview
Problem
Existing clock recovery methods face difficulties in recovering a clock signal from PAM3 signals without a pre-existing clock signal, especially at high data rates, as they require a separate clock signal and struggle with biased mark ratios, making it challenging to maintain signal quality and transmission efficiency.
Innovation Solution
A clock recovery device that converts consecutive symbols of a 2n+1 value PAM signal to an NRZ signal using a signal conversion circuit, allowing clock recovery without a clock signal, by setting threshold voltages and using a hysteresis circuit to achieve a mark ratio of 1/2, enabling efficient clock recovery from PAM3 signals with arbitrary data rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a limiting amplifier is used to convert PAM3 signal to NRZ signal for clock recovery, then the signal can be processed by clock recovery circuit, but the mark ratio becomes biased (not 1/2) making clock recovery difficult
Solution Approach 1:
The patent changes the threshold voltage parameters of the limiting amplifier to properly differentiate PAM3 signal levels. By setting appropriate threshold voltages, the circuit correctly identifies transitions between 0-1 and 1-2 levels, converting them to NRZ signal with proper mark ratio of 1/2, enabling successful clock recovery.
Solution Approach 2:
The patent introduces an intermediate signal conversion stage between the PAM3 signal and the clock recovery circuit. The limiting amplifier acts as an intermediary that converts the trinary PAM3 signal into a binary NRZ signal with balanced mark ratio, making the signal suitable for standard clock recovery circuits that expect NRZ input with 1/2 mark ratio.
2Productivity
If PAM3 signal is input directly to clock recovery circuit, then transmission rate can be maintained, but signal waveform changes slowly at level transitions making phase comparator locking difficult
Solution Approach 1:
The limiting amplifier serves as an intermediary device that receives the PAM3 signal and converts it to NRZ format. This conversion sharpens the signal transitions by creating clean binary levels from the trinary PAM3 levels, providing sufficient edge rate for the phase comparator to lock effectively while preserving the original transmission rate information.
Solution Approach 2:
The patent changes the signal level parameters by converting from three levels (0, 1, 2) in PAM3 to two levels (0, 1) in NRZ. This parameter transformation sharpens the transitions at critical points (0→1 and 1→2), providing the phase comparator with clear locking signals while maintaining the underlying data rate.
3Ease of manufacture
If conventional clock recovery methods are used for PAM3 signals, then existing circuits can be utilized, but a separate clock signal is required which defeats the purpose of clock recovery
Solution Approach 1:
The limiting amplifier with properly set thresholds acts as an intermediary that adapts the PAM3 signal format to match the requirements of conventional NRZ-based clock recovery circuits. This intermediate conversion enables existing circuits to operate on PAM3 signals without requiring a separate input clock, as the converted NRZ signal contains sufficient timing information for self-synchronization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables easy clock recovery from PAM3 signals with arbitrary data rates, eliminating the need for a pre-existing clock signal and maintaining signal quality by converting PAM3 signals to NRZ signals with a balanced mark ratio, thus improving transmission efficiency.
Implementation Method 1
using a hysteresis circuit to achieve a mark ratio of 1/2
Data Source
AI summary
A clock recovery device (10), including: a signal conversion circuit (20) that sequentially converts two consecutive symbols of a 2n+1 value (n is a natural number) pulse amplitude modulation signal to one symbol of an NRZ (Non Return to Zero) signal; and a clock recovery circuit (30) that generates a recovery clock signal from the NRZ signal converted by the signal conversion circuit. The signal conversion circuit converts the two consecutive symbols: to 0, when a second symbol is n−1 or less; to 1, when the second symbol is n+1 or more; to 0, when a first symbol is n−1 or less and the second symbol is n; to 1, when a first symbol is n+1 or more and the second symbol is n; to a conversion result of previous two symbols, when both of the two consecutive symbols are n.