PAM-3 Transceiver Encoding for Higher Bandwidth With Lower Power

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Solution Overview

Problem

Conventional pulse amplitude modulation (PAM) signaling methods, such as PAM-2, PAM-4, and PAM-3, face challenges in increasing bandwidth without causing channel attenuation, clock quality deterioration, and are inefficient in terms of power consumption and occupied area, particularly in high-performance computing applications.

Innovation Solution

A transmitter and receiver design that utilizes PAM-3 signaling with a novel encoding scheme to divide input bits into groups, generating intermediate bit groups and symbol groups with different voltage levels, reducing power consumption and occupied area by parallel encoding and decoding processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If PAM-2 signaling is used to simplify transceiver structure, then device complexity is reduced, but bandwidth increases only one bit per UI requiring higher clock frequency which causes channel attenuation and clock quality deterioration

Engineering Contradiction:
Improvetransceiver structureVSAvoidbandwidth
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent merges multiple bit streams into a single PAM-3 encoded signal path, combining the functionality of multiple parallel PAM-2 channels into one unified channel that achieves equivalent or superior bandwidth without requiring multiple independent transceiver structures

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent changes the signaling parameter from binary (PAM-2) to ternary (PAM-3), fundamentally altering how data is encoded and transmitted. This parameter change enables 1.58 bits per UI transmission rate without proportionally increasing clock frequency, thereby reducing channel attenuation and maintaining clock quality

Inventive Principle:
Principle #35Parameter changes

2Productivity

If PAM-4 signaling is used to transmit two bits per UI, then productivity increases, but sensing margin becomes very small and the system becomes very sensitive to supply voltage noise

Engineering Contradiction:
Improvebits per UIVSAvoidsensing margin
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent changes the signaling parameter from quaternary (PAM-4) to ternary (PAM-3), fundamentally altering how data is encoded and transmitted. This parameter change enables 1.58 bits per UI transmission rate without proportionally increasing clock frequency, thereby reducing channel attenuation and maintaining clock quality

Inventive Principle:
Principle #35Parameter changes

3Productivity

If PAM-3 signaling is used to transmit 1.5849 bits per UI, then productivity increases, but structural inefficiency occurs making it difficult for output driver to maintain impedance matching

Engineering Contradiction:
Improvebits per UIVSAvoidimpedance matching structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the encoding process into distinct functional blocks (encoder, driver, receiver, decoder) with well-defined interfaces. This segmentation allows each block to be independently optimized, particularly the driver stage which can be specifically designed to maintain impedance matching across all PAM-3 signal levels

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the signaling parameter from binary (PAM-2) to ternary (PAM-3), fundamentally altering how data is encoded and transmitted. This parameter change enables 1.58 bits per UI transmission rate without proportionally increasing clock frequency, thereby reducing channel attenuation and maintaining clock quality

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP4270887B1Transmitter and receiver for 3-level pulse amplitude modulation signaling and system including the same
Publication Date: 2026.02.18 SAMSUNG ELECTRONICS CO LTD
  • EP4270887B1 patent drawingFigure 1
  • EP4270887B1 patent drawingFigure 2
  • EP4270887B1 patent drawingFigure 3

AI summary

A transmitter (100) includes an encoder (110) configured to divide a first number of binary input bits of an input data signal into a first bit group (BTG1) and a second bit group (BTG2), generate a first intermediate bit group (IBTG1) and a second intermediate bit group (IBTG2) by manipulating (120) the first bit group and the second bit group differently based on a value of the first bit group, and generate a first symbol group (SG1) and a second symbol group (SG2) by encoding (170,180) the first intermediate bit group and the second intermediate bit group, each of the first symbol group and the second symbol group including a plurality of symbols, and each of the plurality of symbols having three different voltage levels. The transmitter includes a driver (190) configured to generate an output data signal (TX_OUt) by concatenating the first symbol group and the second symbol group.