Pattern-Based PAM-4 Clock Recovery Without 2× Oversampling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing PAM-4 receivers using 2× oversampling clock and data recovery circuits face issues with increased power consumption and jitter due to mismatch problems, and require additional phases, which limits bandwidth and efficiency.
Innovation Solution
A PAM-4 receiver design that employs pattern-based clock and data recovery circuitry, utilizing an analog front end, comparison units with reduced comparators, and a recovery unit to recover clock and data without additional phases, thereby increasing bandwidth and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a 2× oversampling CDR circuit is used in existing PAM-4 signaling, then clock and data recovery can be achieved, but power consumption increases and jitter is more likely to occur due to mismatch problems
Solution Approach 1:
The patent extracts and removes the unnecessary 2× oversampling mechanism from the CDR circuit, implementing instead a baud-rate clock recovery approach that only samples at the essential timing points, thereby eliminating the excess power consumption associated with continuous oversampling while maintaining recovery accuracy
Solution Approach 2:
The patent applies partial action by using only the minimum necessary sampling rate (baud-rate) rather than excessive 2× oversampling, achieving sufficient clock and data recovery performance without the additional power consumption and jitter issues caused by oversampling
2Reliability
If a 2× oversampling CDR circuit is used in existing PAM-4 signaling, then clock and data recovery can be achieved, but jitter increases due to mismatch problems
Solution Approach 1:
The patent removes the 2× oversampling mechanism that introduces mismatch problems and jitter, replacing it with a simplified baud-rate sampling approach that eliminates the source of timing instability while maintaining recovery accuracy through proper timing alignment
Solution Approach 2:
The patent uses exactly the right amount of sampling (baud-rate) without excessive oversampling, avoiding the mismatch problems and jitter that arise from additional sampling phases while still achieving reliable clock and data recovery
3Reliability
If additional phases are used in the CDR circuit, then clock recovery can be achieved, but bandwidth is limited and efficiency decreases
Solution Approach 1:
The patent extracts and removes the additional phase components from the CDR circuit, implementing a straightforward baud-rate clock recovery method that achieves reliable clock synchronization without the bandwidth overhead and efficiency loss associated with multiple sampling phases
Data Source
AI summary
Disclosed in a PAM-4 receiver using pattern-based clock and data recovery circuitry, which includes an analog front end that receives an external signal and recovers channel loss to output a refined PAM-4 signal, a comparison unit that receives the PAM-4 signal and compares the PAM-4 signal with a reference voltage to generate a recovery signal, and a recovery unit that receives the recovery signal and recovers data and a clock. The analog front end includes an equalizer that matches amplitudes of all frequency components of the external signal and an amplifier that amplifies an output signal of the equalizer.