PAM4 Transceiver Clock Recovery and Skew Correction

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Solution Overview

Problem

Existing data communication systems are inadequate for high-speed applications, particularly in handling large amounts of multimedia data, and require improvements in spectral efficiency and power management.

Innovation Solution

A transceiver system that processes incoming data streams, generates a recovered clock signal, and includes a voltage gain amplifier for equalization, track and hold circuits, shift and hold buffer units, ADC modules, and digital signal processors to perform various DSP functions, enabling efficient data transmission in PAM format without a separate equalization module or reference clock.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a separate equalization module is used, then equalization performance is improved, but device complexity and power consumption increase

Engineering Contradiction:
Improveequalization performanceVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent combines the equalization function with the voltage gain amplifier into a single integrated module. The voltage gain amplifier performs both signal amplification and equalization operations simultaneously, eliminating the need for a separate equalization module. This integration reduces device complexity and power consumption while maintaining equalization performance through the use of tap coefficients applied in the voltage domain.

Inventive Principle:
Principle #5Merging (Combining)

2Measurement precision

If a reference clock is used, then clock synchronization is improved, but device complexity and power consumption increase

Engineering Contradiction:
Improveclock synchronizationVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent implements a self-service clock recovery mechanism where the system generates its own clock signal from the incoming data stream without requiring an external reference clock. The clock recovery circuit extracts timing information directly from the received PAM4 signal, and the generated clock is used for sampling and processing. This eliminates the need for a reference clock input, reducing device complexity and power consumption while maintaining synchronization accuracy.

Inventive Principle:
Principle #25Self-service

3Productivity

If multiple separate modules are used for data processing, then processing capability is improved, but power consumption and device complexity increase

Engineering Contradiction:
Improveprocessing capabilityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent integrates multiple data processing functions into unified modules to reduce power consumption and device complexity. The voltage gain amplifier combines amplification and equalization functions. The digital signal processor integrates clock recovery, data sampling, and PAM4 decoding functions. This modular integration approach maintains processing capability while reducing the number of separate components and interconnections, thereby lowering overall power consumption.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent employs multi-functional modules that perform multiple operations within single circuit blocks. The digital signal processor serves as a universal processing unit that handles clock recovery, data sampling, equalization coefficient application, and PAM4 symbol decoding. This multi-functionality reduces the total component count and interconnect complexity, leading to lower power consumption while maintaining comprehensive data processing capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11431416B2PAM4 transceivers for high-speed communication
Publication Date: 2022.08.30 MARVELL ASIA PTE LTD
  • US11431416B2 patent drawing
  • US11431416B2 patent drawing
  • US11431416B2 patent drawing

AI summary

A communication device includes an AFE configured to track and hold a first driving signal to produce a plurality of sample signals, a shift and hold module configured to store the plurality of sample signals, and an ADC configured to respectively convert the plurality of sample signals to a plurality of digitized sample signals, the ADC including a plurality of ADC slices. A DSP is configured to calibrate the AFE based on the plurality of ADC slices corresponding to the plurality of digitized sample signals and generate an output data stream comprising the plurality of digitized samples. A skew management module is configured to detect a skew of the plurality of digitized sample signals in the output data stream generated by the DSP module, generate a programmable skew offset based on the detected skew, and correct the skew in the output data stream based on the programmable skew offset.