PAM-4 Decoder Circuit Segmentation for Power Reduction
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Solution Overview
Problem
Current decoder circuits for PAM-4 signals face challenges in design complexity and high power consumption at high baud rates, particularly due to the difficulty in designing decision circuits and the need for additional two-level combinatorial logic to determine signal levels.
Innovation Solution
A decoder circuit comprising a first decision circuit, a mapping circuit, and optionally a logic circuit, which simplifies the design by generating low and high output signals based on predetermined thresholds and using a rectifier circuit and XNOR truth tables to reduce power consumption and gate count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional decoder circuits with multiple decision circuits and two-level combinatorial logic are used, then decoding accuracy is maintained, but device complexity and power consumption increase significantly at high baud rates
Solution Approach 1:
The patent segments the decoding function into two distinct circuits: a first decision circuit that determines the most significant bit (MSB) by comparing against a first threshold, and a second decision circuit that determines the least significant bit (LSB) by comparing against a second threshold. This segmentation allows each circuit to perform a simplified comparison function rather than requiring complex multi-level logic, thereby reducing overall device complexity while maintaining decoding accuracy.
Solution Approach 2:
The patent introduces an intermediary mapping circuit between the two decision circuits. This mapping circuit receives the PAM-4 signal and generates intermediate signals that are then processed by the decision circuits. The mapping circuit acts as a mediator that transforms the four-level PAM-4 signal into forms that can be efficiently processed by binary decision circuits, simplifying the overall decoding architecture while preserving signal integrity.
2Measurement precision
If traditional decoder circuits with additional two-level combinatorial logic are used, then complete signal level determination is achieved, but power consumption increases at high baud rates
Solution Approach 1:
The patent extracts the threshold comparison function from the complex combinatorial logic and implements it directly in the decision circuits. Each decision circuit independently compares the PAM-4 signal level against its specific threshold to determine the corresponding bit value. This extraction eliminates the need for additional two-level combinatorial logic that would otherwise be required to process the output of multiple comparators, significantly reducing power consumption at high baud rates while maintaining complete signal level determination.
3Reliability
If more decision circuits are added to handle all signal levels, then decoding completeness is improved, but design difficulty and circuit complexity increase
Solution Approach 1:
The patent inverts the traditional approach by having each decision circuit independently determine a bit value based on its own threshold comparison, rather than having multiple decision circuits work together to determine signal levels and then requiring additional logic to combine their outputs. The first decision circuit determines the MSB and the second decision circuit determines the LSB independently, inverting the conventional hierarchical approach and thereby reducing design difficulty while ensuring decoding completeness.
Data Source
AI summary
Disclosed is a decoder circuit for a pulse amplitude modulation signal and a method of decoding a pulse amplitude modulation signal. The pulse amplitude modulation signal has a zeroth signal level, a first signal level, a second signal level and a third signal level. The decoder circuit comprises a first decision circuit, and a mapping circuit. The first decision circuit receives the pulse amplitude modulation signal and generates a low output signal for the first and the zeroth signal level, and generates a high output signal for the third and the second signal level. The mapping circuit receives the pulse amplitude modulation signal and generates a low output signal for the second and first signal level, and generates a high output signal for the third and zeroth signal level. Optionally, the decoder circuit comprises a logic circuit. The logic circuit receives the generated signal of the mapping circuit and the generated signal of the first decision circuit and generates a low output signal or a high output signal according to a predetermined truth table.