PAM-4 Decision-Feedback Equalizer With Early High-Order Symbol Detection

The patent segments the DFE circuit into multiple parallel processing paths, where each path handles a specific combination of prior symbol values. Instead of making multiple sequential tentative decisions, the circuit simultaneously processes different symbol combinations through parallel paths, reducing the computational burden and power consumption while maintaining accurate ISI mitigation.

The patent transitions from a sequential time-based decision process to a parallel spatial processing architecture. By adding the dimension of parallel circuit paths, the system can evaluate multiple symbol combinations simultaneously rather than sequentially, thereby reducing the number of required tentative decisions and associated power consumption.

The patent merges multiple processing functions into shared circuit resources. Common sub-circuits such as delay elements, adders, and comparators are shared across different processing paths through multiplexing and time-division techniques, reducing the total circuit area while maintaining the capability to handle multiple symbol combinations for accurate ISI mitigation.

The patent designs universal circuit blocks that can perform multiple functions depending on the activation signal. For example, a single adder circuit can serve multiple processing paths by being selectively enabled, and delay elements can be shared across different symbol timing positions, thereby reducing overall circuit area while maintaining full functionality for PAM-4 signaling.