Hybrid PAM-4 Driver Calibration for Impedance and Level Linearity

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Solution Overview

Problem

Existing PAM-4 driver calibration systems face challenges in accurately matching termination impedance and reducing non-linearity between signaling levels, leading to inefficiencies in voltage mode and current mode operations.

Innovation Solution

A hybrid voltage mode/current mode PAM-4 transmitter circuit is calibrated using a configurable replica circuit with on-chip termination impedance, enabling precise adjustment of current and voltage levels to match receiver impedance and reduce non-linearity through a calibration control circuit that adjusts the number of enabled output stages and current sourcing/sinking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If voltage mode calibration is performed to match termination impedance, then impedance matching is improved, but non-linearity between signaling levels increases

Engineering Contradiction:
Improvetermination impedance matchingVSAvoidsignaling level linearity
Core Design Contradiction:
Measurement precisionVSManufacturing precision

Solution Approach 1:

The calibration process is segmented into distinct phases: voltage mode calibration for impedance matching followed by current mode calibration for linearity correction. This segmentation allows each calibration mode to address specific aspects independently without interfering with the other, resolving the contradiction between impedance matching and signaling level linearity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically switches between voltage mode and current mode calibration based on the specific calibration objective. The hybrid driver circuit can adapt its operating mode to optimize either impedance matching or signaling level linearity as needed, providing flexible resolution to the technical contradiction.

Inventive Principle:
Principle #15Dynamics

2Manufacturing precision

If current mode enhancement is increased to reduce ratio level mismatch, then signaling level linearity is improved, but power consumption increases

Engineering Contradiction:
Improveratio level mismatch reductionVSAvoidpower consumption
Core Design Contradiction:
Manufacturing precisionVSUse of energy by moving object

Solution Approach 1:

The calibration control circuit adjusts current mode enhancement parameters dynamically during calibration to achieve optimal ratio level mismatch reduction. By carefully controlling the magnitude and timing of current mode adjustments, the system minimizes power consumption while still achieving the desired linearity improvement.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system applies current mode enhancement selectively and partially during calibration rather than continuously at full strength. This partial action approach achieves sufficient ratio level mismatch reduction without unnecessarily increasing power consumption, balancing performance improvement with energy efficiency.

Inventive Principle:
Principle #16Partial or excessive action

3Measurement precision

If hybrid voltage mode/current mode calibration is implemented, then overall calibration accuracy is improved, but device complexity increases

Engineering Contradiction:
Improvecalibration accuracyVSAvoidcalibration circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The hybrid driver circuit is designed with multi-functionality, serving both voltage mode and current mode operations within a single integrated structure. This universality reduces the need for separate dedicated circuits for each calibration mode, thereby limiting the increase in device complexity while still achieving high calibration accuracy.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The calibration control circuit acts as an intermediary that coordinates between voltage mode and current mode calibration processes. It manages the switching and parameter adjustment between modes, simplifying the overall control logic and reducing the complexity burden that would otherwise arise from implementing both calibration modes independently.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10841138B2PAM-4 calibration
Publication Date: 2020.11.17 CADENCE DESIGN SYST INC
  • US10841138B2 patent drawing
  • US10841138B2 patent drawing
  • US10841138B2 patent drawing

AI summary

A hybrid voltage mode (VM) and current mode (CM) four-level pulse amplitude modulation (PAM-4) transmitter circuits (a.k.a. drivers) is calibrated using a configurable replica circuit and calibration control circuitry. The replica circuit includes an on-chip termination impedance to mimic a receiver's termination impedance. The amount of level enhancement provided by the current mode circuitry is calibrated by adjusting the current provided to the output node and sunk from the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving an intermediate PAM-4 level. After the level enhancement has been set, the non-linearity between levels is calibrated by adjusting the amount of current provided to the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving a maximum output voltage level.