PAM-4 Encoding Schemes for Signal Noise Reduction

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Solution Overview

Problem

High bandwidth serial data buses using Pulse Amplitude Modulation (PAM) are vulnerable to interference, leading to reduced signal-to-noise ratio (SNR) due to increased voltage-level distinctions, which can be mitigated but at the cost of additional metadata wires and bandwidth overhead.

Innovation Solution

Conditional PAM-424 encoding, which selectively uses a two-level symbol bridge between four-level symbols to eliminate high voltage deltas, reducing noise without requiring a separate metadata wire, by inserting a two-level symbol bridge only when specific conditions are met, such as transitions between extreme voltage levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If PAM-4 encoding is used to double bandwidth, then data transmission rate is improved, but signal-to-noise ratio deteriorates due to reduced voltage-level distinction

Engineering Contradiction:
Improvedata transmission rateVSAvoidsignal-to-noise ratio
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the voltage level transitions by inserting two-level bridge symbols between four-level PAM-4 symbols. This segmentation reduces the maximum voltage delta from 3ΔV to 1ΔV, mitigating noise and coupling effects while maintaining the high bandwidth benefits of PAM-4 encoding

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces two-level bridge symbols as intermediary elements between four-level PAM-4 symbols. These bridge symbols act as mediators that reduce voltage transitions and minimize noise coupling between adjacent data lanes, improving signal integrity without sacrificing bandwidth

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If Data Bus Inversion (DBI) is used to reduce voltage transitions, then noise is reduced, but device complexity increases due to additional metadata wire

Engineering Contradiction:
ImprovenoiseVSAvoidnumber of wires
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent merges the noise reduction function into the existing data lanes by selectively inserting two-level bridge symbols based on data patterns. This eliminates the need for a separate DBI metadata wire, reducing device complexity while maintaining noise reduction benefits

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The encoding scheme uses the data bits themselves to control the insertion of bridge symbols, making the noise reduction mechanism self-regulating. The transmitter and receiver use shared knowledge of the encoding rules to automatically insert and detect bridge symbols without requiring external control signals

Inventive Principle:
Principle #25Self-service

3Object-affected harmful factors

If two-level bridge symbols are inserted to eliminate 3ΔV transitions, then noise is reduced, but bandwidth efficiency deteriorates

Engineering Contradiction:
ImprovenoiseVSAvoidbandwidth efficiency
Core Design Contradiction:
Object-affected harmful factorsVSProductivity

Solution Approach 1:

The patent applies partial action by inserting two-level bridge symbols only when specific data patterns are detected (e.g., transitions between extreme voltage levels). This selective insertion reduces noise where necessary while minimizing bandwidth overhead by avoiding unnecessary bridge symbol insertions

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10599606B2424 encoding schemes to reduce coupling and power noise on PAM-4 data buses
Publication Date: 2020.03.24 NVIDIA CORP
  • US10599606B2 patent drawing
  • US10599606B2 patent drawing
  • US10599606B2 patent drawing

AI summary

Methods of operating a serial data bus generate two-level bridge symbols to insert between four-level symbols on one or more data lanes of the serial data bus, to reduce voltage deltas on the one or more data lanes during data transmission on the serial data bus.