PAM4 Error Measurement With EIEOS Masking for PCIe 6.0 Flits
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Solution Overview
Problem
The introduction of FEC in PCI Express 6.0 results in the absence of an electrical idle exit ordered set (EIEOS) required for 1b/1b synchronization, preventing effective error measurement in the PCIe Gen6 physical layer, as existing error rate measurement apparatuses cannot receive EIEOS from the device under test.
Innovation Solution
An error rate measurement apparatus and method that includes generating a PAM4 signal with an EIEOS and SKP OS, masking unnecessary patterns, detecting FEC symbol errors, and determining Flit errors by setting threshold values, allowing synchronization management and accurate error detection without transitioning the device to the L0 state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FEC is introduced in PCI Express 6.0, then error correction capability is improved, but 1b/1b synchronization becomes impossible without EIEOS
Solution Approach 1:
The patent applies preliminary action by pre-inserting EIEOS patterns into the Flit pattern at specific positions before transmission. The operation unit configures the Flit pattern to include EIEOS at predetermined locations, ensuring that the device under test can perform 1b/1b synchronization even though the normal L0 state Flit pattern does not include EIEOS. This resolves the contradiction by proactively providing the synchronization signal needed for FEC-guarded patterns.
2Productivity
If only Flit pattern is transmitted in L0 state, then normal data transmission is maintained, but EIEOS cannot be received for synchronization
Solution Approach 1:
The patent merges two previously separate functions into a single Flit pattern configuration: normal data transmission (Flit) and synchronization signal transmission (EIEOS). The operation unit configures the Flit pattern to include both Flit data and EIEOS at specific positions, allowing the device under test to simultaneously perform data transmission and 1b/1b synchronization using the same transmitted signal, thereby resolving the contradiction between maintaining data transmission and enabling synchronization.
3Measurement precision
If mask pattern is applied to mask SKP OS and EIEOS portions, then accurate Flit error detection is enabled, but measurement complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the received signal into distinct segments: Flit portions and non-Flit portions (SKP OS and EIEOS). The symbol mask generation unit generates mask patterns that correspond to these segmented portions, allowing the error detection unit to selectively apply error detection only to Flit portions while ignoring non-Flit portions. This segmented approach enables accurate Flit error detection without requiring complex overall measurement system redesign.
Data Source
AI summary
In an error detector 4, a symbol mask generation unit 27 generates a mask pattern, an error detection unit 30 detects and counts an error in a portion corresponding to Flit in a PAM4 signal from a device under test W, and a Flit error detection unit 31 detects and counts an FEC symbol error in a portion corresponding to Flit for each ECC group, and determines in which the number of FEC symbol errors exceeds a threshold value to be a Flit error.