PAM4 Memory Receiver Feedback Circuits for ISI Reduction
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Solution Overview
Problem
Memory devices face challenges with inter-symbol interference (ISI) in multi-level signaling, leading to decreased channel utilization efficiency and increased latency due to the use of more circuit elements and increased power consumption, especially when employing four-level pulse amplitude modulation (PAM4) schemes.
Innovation Solution
The implementation of a multi-phase architecture with a plurality of peaking circuits and feedback circuits in memory devices to decode signals modulated using PAM4, reducing ISI by processing incoming signals in parallel and using active inductor configurations to reshape the signal, thereby increasing channel bandwidth and reducing energy transfer to subsequent bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If PAM4 multi-level signaling is used to increase data rate, then channel bandwidth utilization is improved, but inter-symbol interference increases and signal detection becomes more difficult
Solution Approach 1:
The patent implements decision feedback equalization (DFE) where previous symbol decisions are fed back to compensate for inter-symbol interference in current symbol detection. The feedback circuit uses previously decoded symbols to generate compensation signals that are subtracted from the received signal, thereby reducing ISI and improving detection accuracy in PAM4 multi-level signaling
Solution Approach 2:
The patent divides the signal processing into multiple phases (first phase, second phase, third phase) where each phase processes specific voltage level comparisons. This segmentation allows parallel processing of multiple voltage threshold comparisons, improving detection speed and accuracy while managing the complexity of PAM4 signal interpretation
2Reliability
If more circuit elements are used to reduce ISI, then signal integrity is improved, but device complexity and power consumption increase
Solution Approach 1:
The circuit is divided into multiple phases with each phase handling specific voltage level comparisons. This segmentation allows the use of simpler comparator circuits in each phase rather than one complex high-speed circuit, reducing overall device complexity while maintaining signal integrity through parallel processing
Solution Approach 2:
The patent implements three separate voltage level comparison circuits that perform partial actions on the signal. Each comparator checks against a specific reference voltage level, and their combined results provide complete symbol detection. This partial action approach distributes the computational burden across multiple simpler circuits rather than one complex circuit
3Measurement precision
If more circuit elements are used to improve signal detection, then detection accuracy is improved, but power consumption increases
Solution Approach 1:
The patent uses three separate voltage comparison circuits that each perform a partial detection function. By distributing the detection task across multiple specialized comparators rather than one high-power general-purpose circuit, the system achieves high detection accuracy while managing power consumption through functional specialization and parallel operation at lower individual power levels
Data Source
AI summary
Methods, systems, and devices for feedback for multi-level signaling in a memory device are described. A receiver may use a modulation scheme to communicate information with a host device. The receiver may include a first circuit, a second circuit, a third circuit, and a fourth circuit. Each of the first circuit, the second circuit, the third circuit, and the fourth circuit may determine, for a respective clock phase, a voltage level of a signal modulated using the modulation scheme. The receiver may include a first feedback circuit, a second feedback circuit, a third feedback circuit, and a fourth feedback circuit. The first feedback circuit that may use information received from the first circuit at the first clock phase and modify the signal input into the second circuit for the second clock phase.