PAM4 Memory Signal Calibration for Uniform Level Separation

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Solution Overview

Problem

Current memory devices face challenges in maintaining identical signal level intervals during high-capacity and high-speed data transmissions, particularly with PAM4 signaling, leading to gaps between signal levels that are not identical, which can decrease signal sensing margins.

Innovation Solution

A memory device with a Ratio of Level Separation Mismatch (RLM) controller that adjusts gaps between signal levels using a ZQ calibration and additional code calibrations, ensuring identical signal level intervals through a transceiver configured for multilevel signaling, including comparators, code generators, and drivers to manage pull-up and pull-down resistances.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If PAM4 signaling is used for high-capacity and high-speed data transmissions, then data transmission capacity and speed are improved, but signal level intervals become non-identical leading to decreased signal sensing margins

Engineering Contradiction:
Improvedata transmission capacity and speedVSAvoidsignal sensing margin
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent adjusts driver strengths as a variable parameter to compensate for non-identical signal level intervals in PAM4 signaling. By dynamically changing driver strength parameters, the system maintains identical signal level intervals despite the inherent limitations of PAM4 signaling, thus preserving signal sensing margins while enabling high-capacity and high-speed data transmission

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces physical adjustment of signal levels with a calibration system that uses code generation and comparison logic. Instead of mechanically adjusting signal intervals, the system uses digital calibration processes involving comparators, code generators, and lookup tables to achieve identical signal level intervals through logical control of driver strengths

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Device complexity

If driver strengths are not calibrated, then device complexity is reduced, but signal level intervals become non-identical causing data transmission errors

Engineering Contradiction:
Improvecalibration circuit complexityVSAvoidsignal level interval consistency
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent performs calibration actions before actual data transmission. The calibration process pre-determines appropriate driver strengths by comparing signal levels and generating calibration codes, storing these in lookup tables. This preliminary calibration ensures that when data transmission begins, the drivers are already optimized to produce identical signal level intervals, preventing transmission errors

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces calibration codes and lookup tables as intermediary elements between the drivers and the signal levels. These intermediaries store the relationship between driver strengths and signal level intervals, allowing the system to achieve precise signal level control without direct complex control logic during data transmission, thus balancing complexity and precision

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11782618B2Memory device, method of calibrating signal level thereof, and memory system having the same
Publication Date: 2023.10.10 SAMSUNG ELECTRONICS CO LTD
  • US11782618B2 patent drawing
  • US11782618B2 patent drawing
  • US11782618B2 patent drawing

AI summary

A method of calibrating a signal level of a memory device includes performing pull-up code and pull-down code calibrations, using a ZQ calibration for non-return-to-zero (NRZ) signaling, performing a most significant bit (MSB) code calibration, using an MSB additional driver for pulse amplitude modulation level-4 (PAM4) signaling, and performing a least significant bit (LSB) code calibration using an LSB additional driver for the PAM4 signaling.