PAM4 Memory Signal Calibration for Uniform Level Gaps

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Solution Overview

Problem

Current memory systems face challenges in maintaining identical signal gaps for high-speed and high-capacity data transmissions using PAM4 signaling, leading to decreased signal sensing margins due to driver strength variations and gds distortion.

Innovation Solution

The implementation of a Ratio of Level Mismatch (RLM) controller that adjusts and compensates signal level gaps through ZQ-calibration and additional driver calibration, ensuring identical gaps between PAM4 signal levels by freely setting reference voltages and performing calibration after pull-up/pull-down code calibration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If PAM4 signaling is used for high-speed and high-capacity data transmission, then data transmission capacity and speed are improved, but signal sensing margins decrease due to driver strength variations and gds distortion

Engineering Contradiction:

Improvedata transmission capacity and speedVSAvoidsignal sensing margins

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies parameter changes by adjusting the reference voltage levels (Vref1 and Vref2) to compensate for gds distortion. The RLM controller dynamically modifies voltage parameters to maintain equal signal gaps between PAM4 levels, thereby preserving signal sensing margins while enabling high-speed data transmission

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent implements feedback through the RLM controller that continuously monitors signal levels and adjusts reference voltages accordingly. The controller uses feedback from signal gap measurements to dynamically correct driver strength variations and maintain optimal signal integrity for PAM4 transmission

Inventive Principle:

Principle #23Feedback

2Reliability

If driver strength is increased to compensate for signal loss, then signal sensing margins are improved, but gds distortion increases leading to non-identical signal gaps

Engineering Contradiction:

Improvesignal sensing marginsVSAvoidsignal gap uniformity

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent uses parameter changes by adjusting reference voltage levels (Vref1 and Vref2) to compensate for gds distortion. The RLM controller dynamically modifies voltage parameters to maintain equal signal gaps between PAM4 levels, thereby preserving signal sensing margins while enabling high-speed data transmission

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent applies preliminary action by performing RLM calibration before actual data transmission. The RLM controller pre-adjusts reference voltages to counteract anticipated gds distortion and driver strength variations, ensuring optimal signal gap uniformity is established before high-speed PAM4 transmission begins

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentEP3968327B1Memory device, method of calibrating signal level thereof, and memory system having the same

Publication Date: 2024.04.10 SAMSUNG ELECTRONICS CO LTD

Figure 1
Figure 2A(a)~2A(b)
Figure 2B~2C

AI summary

A method of calibrating a signal level of a memory device includes performing pull-up code and pull-down code calibrations, using a ZQ calibration for non-return-to-zero (NRZ) signaling, performing a most significant bit (MSB) code calibration, using an MSB additional driver for pulse amplitude modulation level-4 (PAM4) signaling, and performing a least significant bit (LSB) code calibration using an LSB additional driver for the PAM4 signaling.