PAM-4 Receiver Clock Recovery With Jitter Compensation
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Solution Overview
Problem
Current high-speed data transmission systems, particularly in 5G communications and high-performance computing, face challenges in jitter tolerance and synchronization due to uncorrelated jitter between clock and data signals, which existing solutions inadequately address, especially at data rates exceeding 50 Gb/s with PAM-4 signaling.
Innovation Solution
A 60-Gb/s ¼-rate PAM-4 receiver with a jitter compensation clock and data recovery (JCCDR) system, employing a first-order delay-locked loop and a second-order wideband phase-locked loop, along with a jitter compensation circuit that detects and inverts the loop filter voltage to attenuate jitter transfer, achieving a wide jitter tolerance bandwidth of 40 MHz and ultralow jitter transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional clock and data recovery system is used, then the system structure is simple, but the jitter tolerance bandwidth is narrow and cannot handle uncorrelated jitter between clock and data signals
Solution Approach 1:
The patent segments the clock and data paths into separate lanes with independent processing. The clock lane includes a buffer and duty cycle correction block, while the data lane includes an equalizer and deskew circuit. This segmentation allows independent optimization of each path to handle uncorrelated jitter effectively.
Solution Approach 2:
The patent introduces an intermediary deskew circuit that processes the data signal to compensate for phase skew relative to the clock signal. This intermediary component acts as a mediator between the clock and data paths, aligning their phases and reducing the impact of uncorrelated jitter without requiring complex restructuring of the entire system.
2Productivity
If the data rate is increased to over 50 Gb/s with PAM-4 signaling, then the transmission capacity is improved, but the signal quality becomes increasingly susceptible to jitter
Solution Approach 1:
The patent applies preliminary equalization to the data signal before it reaches the deskew circuit and decoder. The equalizer pre-compensates for channel effects and potential jitter, preparing the signal for subsequent processing. This preliminary action reduces the impact of high-frequency jitter that becomes more significant at data rates over 50 Gb/s.
Solution Approach 2:
The patent changes the signaling parameter from traditional NRZ to PAM-4 modulation, which increases data capacity but also increases susceptibility to jitter. To compensate, the system adjusts other parameters including introducing a deskew circuit with adjustable delay and implementing a dual-path architecture that allows independent optimization of clock and data recovery parameters.
3Measurement precision
If multiple components (channel, equalizer, buffer, DCC, IJO/MPLL, PI) are cascaded, then the signal processing capability is improved, but the unfolded phase skew reaches several UIs
Solution Approach 1:
The patent implements a feedback mechanism where the deskew circuit continuously monitors the phase relationship between clock and data signals and adjusts its delay accordingly. The decoder detects phase errors and feeds this information back to the deskew circuit, which compensates for the accumulated phase skew from cascaded components, reducing the overall phase skew to minimal levels.
Data Source
AI summary
A PAM-4 receiver with jitter compensation clock and data recovery is provided. The receiver includes a first-order delay-locked loop (DLL) which employs a bang-bang phase detector (BBPD) and a voltage-controlled delay line (VCDL) circuit supporting 40 MHz jitter tracking bandwidth and static phase skew elimination. A second-order wideband phase-locked loop (WBPLL) using the ¼-rate reference clock provides multi-phase clock generation with low input-to-output latency. To suppress the consequent jitter transfer, a jitter compensation circuit (JCC) acquires the jitter transfer amplitude and frequency information by detecting the DLL loop filter voltage (VLF(s)) signal, and generates an inverted loop filter voltage signal, denoted as VLFINV(s). The VLFINV(s) modulates a group of complementary VCDLs (C-VCDLs) to attenuate the jitter transfer on both recovered clock and data. With the provided receiver, a jitter compensation ratio up to 60% can be supported from DC to 4 MHz, with a −3-dB corner frequency of 40 MHz.