PAM-4 Transmitter De-Emphasis for High-Speed Link Equalization

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

High-speed serial interfaces face challenges in ensuring reliable data transmission due to variations in circuit design, component manufacture, and environmental conditions, leading to suboptimal transmitter and receiver equalization mechanisms that result in 'good enough' compensation solutions rather than optimal ones, requiring extensive iterative processes for link training.

Innovation Solution

A de-emphasis circuit and channel management module are implemented in the transmitter and receiver, respectively, to adjust signal levels and compensation values based on bit error rate, using quaternary pulse amplitude modulation (PAM-4) schemes and back channel adaptation to optimize data transmission, particularly for high-speed serial channels beyond 32 Gbps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional equalization mechanisms are used, then implementation is simpler, but transmission reliability deteriorates at high speeds beyond 32 Gbps

Engineering Contradiction:
Improvetransmission reliabilityVSAvoidequalization mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic equalization adjustment by continuously monitoring bit error rates and adapting de-emphasis levels in real-time during data transmission. The equalization parameters are not fixed but dynamically adjusted based on actual channel conditions, allowing the system to maintain optimal performance across varying speeds and environmental conditions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system employs feedback mechanisms where the receiver measures bit error rates and transmits this information back to the transmitter. The transmitter then adjusts its de-emphasis levels based on this feedback, creating a closed-loop control system that continuously optimizes equalization for the specific channel conditions.

Inventive Principle:
Principle #23Feedback

2Measurement precision

If iterative link training processes are used, then equalization accuracy is improved, but training time increases

Engineering Contradiction:
Improveequalization accuracyVSAvoidlink training time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs preliminary equalization adjustments during the link training phase by testing different de-emphasis levels and selecting the optimal configuration before actual data transmission begins. This preliminary optimization reduces the need for extensive iterative adjustments during operation, thereby reducing overall training time while maintaining accuracy.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system systematically varies key parameters such as de-emphasis levels across a range of values during link training, measuring performance at each setting to identify the optimal configuration. This structured parameter exploration enables accurate equalization selection without requiring exhaustive iterative processes during active transmission.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If de-emphasis levels are adjusted for optimal performance, then bit error rate improves, but circuit complexity increases

Engineering Contradiction:
Improvebit error rateVSAvoidde-emphasis circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies different de-emphasis levels to different signal components and time periods based on local channel conditions. Rather than using a uniform complex equalization approach throughout, the system selectively adjusts de-emphasis for specific signal transitions and time intervals where they are most needed, achieving improved bit error rates with minimal additional circuit complexity.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10581652B1System and method for PAM-4 transmitter bit equalization for improved channel performance beyond 32 Gbps
Publication Date: 2020.03.03 DELL PROD LP
  • US10581652B1 patent drawing
  • US10581652B1 patent drawing
  • US10581652B1 patent drawing

AI summary

A serial data channel includes a transmitter that encodes serial data using a quaternary PAM-4 scheme, wherein the four PAM-4 signal levels include two balanced pairs of differential signal levels. The channel includes a de-emphasis circuit that determines that first and second symbols are in a first PAM-4 state, that a third symbol is in a second PAM-4 state, and provides a first de-emphasis to a voltage level of the second symbol in response to determining that the third symbol is represented as the second state. The de-emphasis circuit further determines that fourth and fifth symbols are in the second state, that a sixth symbol is in the first state, and provides a second de-emphasis to a voltage level of the fifth symbol in response to determining that the sixth symbol is represented as the first state. The first de-emphasis and the second de-emphasis represent different de-emphasis levels.