Pan-Shaped Electrode PCRAM for Low Reset Current
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Solution Overview
Problem
Manufacturing high-density phase change memory devices with small dimensions and low reset currents is challenging due to tight process variation specifications needed for large-scale memory devices, and existing methods struggle to achieve compatibility with peripheral circuits on integrated circuits.
Innovation Solution
A phase change random access memory (PCRAM) device is developed with a pan-shaped electrode member and thin film bridge of programmable resistive material, where the active volume of memory material is defined by the thickness of the insulating wall, the thin film bridge, and the side wall electrode structures, allowing for small reset currents and low power consumption, and the manufacturing process involves photoresist trimming and isotropic etching to achieve sub-lithographic feature sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the size of the phase change material element and contact area are reduced to achieve low reset currents, then the reset current magnitude is reduced, but the manufacturing precision requirements become tighter due to small dimensions
Solution Approach 1:
The patent transitions from planar electrode structures to three-dimensional pan-shaped electrode members with vertical side walls. This dimensional change allows the active area to be confined in the horizontal plane (reducing reset current) while providing sufficient vertical height for reliable electrical contact and phase change material containment, effectively decoupling the conflicting requirements of small contact area and manufacturing tolerability.
Solution Approach 2:
The patent changes the geometric parameters of the electrode structure by introducing a pan-shaped configuration with specific aspect ratios between the base area and side wall height. This parameter optimization allows the device to achieve low reset currents through reduced planar contact area while maintaining manufacturability through adequate vertical dimensions that are less sensitive to lithographic variations.
2Productivity
If very small dimensions are used to achieve high density memory, then the reset current is reduced, but the compatibility with peripheral circuits becomes difficult
Solution Approach 1:
The patent segments the electrode structure into distinct functional regions: a small planar base area for low reset current operation, and extended vertical side walls for electrical connection. This segmentation allows the memory element to operate at high density while the side wall structures provide standardized interfaces that are compatible with peripheral circuit interconnects, effectively bridging the scale gap between high-density memory cells and standard peripheral circuits.
Solution Approach 2:
The pan-shaped electrode member nests the small active phase change material volume within a larger three-dimensional structure. The nested configuration allows the core memory function to operate at very small dimensions for high density, while the outer shell of side wall structures provides the mechanical and electrical interface dimensions needed for compatibility with standard peripheral circuit pitch and interconnect dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The PCRAM device achieves very small reset currents and low power consumption while being easily manufacturable, meeting the requirements for large-scale memory devices and compatibility with peripheral circuits.
Implementation Method 1
Phase change based memory materials have at least two solid phases, including for example a generally amorphous solid phase and a generally crystalline solid phase
Implementation Method 2
The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure
Implementation Method 3
photoresist trimming and isotropic etching to achieve sub-lithographic feature sizes
Data Source
AI summary
A memory device comprising a first pan-shaped electrode having a side wall with a top side, a second pan-shaped electrode having a side wall with a top side and an insulating wall between the first side wall and the second side wall. The insulating wall has a thickness between the first and second side walls near the respective top sides. A bridge of memory material crosses the insulating wall, and defines an inter-electrode path between the first and second electrodes across the insulating wall. An array of such memory cells is provided. The bridges of memory material have sub-lithographic dimensions.