Multilayer Panel Array With Waveguide Cages for RF Isolation

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Solution Overview

Problem

Current phased array antennas are costly, large, heavy, and have limited bandwidth and polarization diversity, making them unsuitable for widespread military and commercial applications due to high production costs and complex fabrication processes.

Innovation Solution

A method for fabricating a panel array using a multilayer printed wiring board (PWB) with a single lamination step, incorporating flip-chip circuits and waveguide cages for improved RF performance, and utilizing a balanced feed slot for polarization diversity, which simplifies the fabrication process and reduces costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple sub-assemblies are combined to provide mixed signal multilayer PWB, then circuit functionality is improved, but fabrication complexity and cost increase due to multiple process step-cycles

Engineering Contradiction:
Improvecircuit functionalityVSAvoidfabrication complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines RF circuits and digital circuits onto a single PWB substrate, eliminating the need for multiple separate sub-assemblies. This merging approach maintains full circuit functionality while reducing fabrication complexity from multiple process step-cycles to a single integrated fabrication process.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If back-drill and back-fill operations are performed on RF via holes, then RF performance is improved, but cost increases and performance degrades due to tolerances and trapped air pockets

Engineering Contradiction:
ImproveRF performanceVSAvoidmanufacturing cost and complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent extracts and eliminates the problematic back-drill and back-fill operations from the fabrication process. By using a different via structure design, the patent achieves improved RF performance without incurring the additional costs and performance degradation associated with traditional back-drill and back-fill methods.

Inventive Principle:
Principle #2Taking out (Extraction)

3Ease of manufacture

If LTCC materials are used for multilayer laminate, then fabrication is simplified to one lamination step, but RF performance degrades due to lossy conductive paste and higher dielectric constant

Engineering Contradiction:
Improvefabrication simplicityVSAvoidRF performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent changes the material parameters by using standard PTFE-based materials instead of LTCC materials. This parameter change maintains excellent RF performance characteristics while accepting the trade-off of multiple lamination steps, as the RF performance benefits outweigh the additional fabrication complexity.

Inventive Principle:
Principle #35Parameter changes

4Volume of moving object

If phased array antenna size is reduced for compactness, then portability is improved, but bandwidth and polarization diversity requirements become more difficult to meet

Engineering Contradiction:
Improveantenna sizeVSAvoidbandwidth and polarization diversity
Core Design Contradiction:
Volume of moving objectVSAdaptability or versatility

Solution Approach 1:

The patent transitions from planar circuit layouts to three-dimensional stacked circuit configurations. By utilizing multiple layers and vertical interconnections, the patent achieves compact antenna size while maintaining sufficient bandwidth and polarization diversity through the additional dimensional space provided by the stacked architecture.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentEP2412056B1Panel array
Publication Date: 2013.09.18 RAYTHEON CO
  • EP2412056B1 patent drawingFigure 1
  • EP2412056B1 patent drawingFigure 1A
  • EP2412056B1 patent drawingFigure 1B

AI summary

A mixed-signal, multilayer printed wiring board fabricated in a single lamination step is described. The PWB includes one or more radio frequency (RF) interconnects between different circuit layers on different circuit boards which make up the PWB. The PWB includes a number of unit cells with radiating elements and an RF cage disposed around each unit cell to isolate the unit cell. A plurality of flip-chip circuits are disposed on an external surface of the PWB and a heat sink can be disposed over the flip chip components.