Panel-Level Circuit Alignment for Shifted Semiconductor Dies
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Solution Overview
Problem
Current panel-level semiconductor packaging methods face challenges due to semiconductor dies shifting away from their designed positions during bonding and molding processes, complicating subsequent steps like forming a circuit layer.
Innovation Solution
A method involving the generation of a die location check (DLC) file to determine true positions of semiconductor dies, aligning green circuit files to these positions, and forming the circuit layer accordingly, ensuring precise placement and alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor dies are bonded onto a panel and a molding layer is formed for encapsulation, then the semiconductor devices are protected and packaged, but the semiconductor dies shift away from their designed positions
Solution Approach 1:
The patent performs a post-bonding inspection to detect the actual positions of semiconductor dies before forming the molding layer. This preliminary detection allows the system to calculate shift amounts and generate a die location check (DLC) file that compensates for positional deviations, ensuring accurate alignment in subsequent circuit layer formation processes.
2Reliability
If a molding layer is formed to encapsulate semiconductor devices, then the devices are protected, but subsequent processes such as forming a circuit layer become difficult due to die shifts
Solution Approach 1:
The patent implements a feedback mechanism where the actual positions of semiconductor dies are detected through post-bonding inspection, and this information is used to generate a DLC file. The DLC file provides corrected position data that is fed into the circuit layer formation process, enabling accurate manufacturing despite die shifts that occur during bonding and molding.
3Productivity
If multiple processes are performed for bonding and molding, then semiconductor devices are packaged, but die positions shift from green positions
Solution Approach 1:
The patent performs a post-bonding inspection to detect the actual positions of semiconductor dies before forming the molding layer. This preliminary detection allows the system to calculate shift amounts and generate a die location check (DLC) file that compensates for positional deviations, ensuring accurate alignment in subsequent circuit layer formation processes.
Solution Approach 2:
The patent implements a feedback mechanism where the actual positions of semiconductor dies are detected through post-bonding inspection, and this information is used to generate a DLC file. The DLC file provides corrected position data that is fed into the circuit layer formation process, enabling accurate manufacturing despite die shifts that occur during bonding and molding.
Data Source
AI summary
A method is disclosed for forming a circuit layer on diverse semiconductor devices, including semiconductor dies and passive packages, within an electronic module. The method comprises generating a Die Location Check (DLC) file to store true positions of the semiconductor devices on a reconstructed panel, Next, a green circuit file specifying the intended positions for the semiconductor devices on the circuit layer is retrieved. Using the DLC file, these intended positions are then adjusted to match the true positions, resulting in an adapted circuit file. Finally, this adapted file guides the formation of the circuit layer, ensuring it aligns precisely with the semiconductor devices. The present application also discloses a method of generating a DLC file for determining true positions of a plurality of semiconductor devices in a reconstructed panel. The present application further discloses a panel-level semiconductor packaging method for making a plurality of electronic modules.