Panel Form Carrier Semiconductor Package Interconnect
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Solution Overview
Problem
Conventional semiconductor packaging methods, particularly for leadframe ball array packages like QFNs, face challenges in achieving a simple and cost-effective vertical electrical interconnect due to time-consuming plating processes that are susceptible to defects, leading to reduced manufacturing yield and increased costs.
Innovation Solution
A method involving a panel form carrier with insulating and conductive layers, where a semiconductor die is mounted to the conductive layer with bond wires formed between the die and the layer, and an encapsulant is deposited before removing the carrier and parts of the insulating layer to expose the conductive layers for electrical isolation, thereby minimizing bond wire span and enhancing interconnect efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional plating process is used to form conductive vias for vertical electrical interconnect, then electrical connection is achieved, but the process is time-consuming and susceptible to voids and defects
Solution Approach 1:
The patent extracts the problematic plating process from the manufacturing flow and replaces it with a deposition-based approach. Conductive layers are formed by depositing material over the carrier surface, eliminating the time-consuming and defect-prone plating process while maintaining electrical connectivity functionality.
Solution Approach 2:
The patent substitutes the electrochemical plating process with a physical deposition process. Instead of using electrochemical reactions to build conductive vias, the invention uses deposition techniques to form conductive layers directly, replacing a complex chemical-mechanical system with a simpler physical process.
2Reliability
If conventional plating process is used to form conductive vias, then electrical connection is achieved, but voids and defects are introduced that reduce manufacturing yield
Solution Approach 1:
The patent replaces the electrochemical plating mechanism with a deposition-based approach that provides better control over material placement. This substitution eliminates the void formation and defects inherent in plating processes, achieving both electrical connectivity and high manufacturing precision without compromising yield.
Solution Approach 2:
The conductive layers are formed in advance over the carrier surface before die mounting and encapsulation. This preliminary formation of conductive structures allows for better quality control and eliminates the need for subsequent via formation that could introduce defects, thereby improving both manufacturing precision and yield.
3Ease of manufacture
If carrier is retained throughout the process, then structural support is provided, but additional removal steps are required increasing process complexity
Solution Approach 1:
The carrier is designed with built-in release features that allow for automatic or facilitated removal after the die is mounted and encapsulated. The preliminary design of the carrier-release mechanism eliminates the need for complex manual removal procedures, reducing process complexity while maintaining ease of manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the interconnect process, reduces manufacturing costs, and improves yield by minimizing defects and bond wire span, resulting in a more efficient and cost-effective semiconductor package.
Implementation Method 1
forming an insulating layer over the carrier
Implementation Method 2
forming a first conductive layer over the insulating layer, forming a second conductive layer over the first conductive layer
Implementation Method 3
depositing a first encapsulant over the first semiconductor die and carrier
Data Source
AI summary
A semiconductor device has a first insulating layer formed over a carrier. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer. Vias are formed through the second insulating layer. A second conductive layer is formed over the second insulating layer and extends into the vias. A semiconductor die is mounted to the second conductive layer. A bond wire is formed between a contact pad on the semiconductor die and the second conductive layer. The second conductive layer extends to a mounting site of the semiconductor die to minimize the bond wire span. An encapsulant is deposited over the semiconductor die. A portion of the first insulating layer is removed to expose the second conductive layer. A portion of the first conductive layer is removed to electrically isolate remaining portions of the first conductive layer.