Panel-Level Multi-Die HPC Packaging Beyond Wafer Size Limits
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Solution Overview
Problem
High-performance computing (HPC) faces challenges in achieving zettascale performance due to limitations in wafer-level system integration, including size constraints and yield issues, which hinder the development of efficient packaging architectures that can meet the demands of high interconnect density, bandwidth, and power efficiency.
Innovation Solution
The implementation of panel-level components and systems using panel-level manufacturing techniques, which allow for the assembly of multiple integrated circuit dies on a single substrate with interconnects, enabling larger form factors and increased mechanical stiffness through glass reinforcement layers, and supporting advanced interconnect structures and thermal management solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer-level system integration is used, then manufacturing efficiency is improved, but size constraints and yield issues prevent achieving zettascale performance
Solution Approach 1:
The system is divided into multiple independent panels that can be manufactured separately using wafer-level techniques, then assembled into a larger zettascale computing system. This allows maintaining manufacturing efficiency while achieving the required system size through modular panel assembly.
Solution Approach 2:
The patent transitions from two-dimensional wafer-level integration to three-dimensional panel-level integration by stacking multiple panels vertically and using through-panel interconnects. This enables scaling to zettascale performance while maintaining manufacturing efficiency through standardized panel modules.
2Area of stationary object
If panel-level integration is used to increase area, then mechanical stability deteriorates without reinforcement
Solution Approach 1:
The patent employs composite panel structures combining multiple materials (substrate materials, dielectric layers, conductive interconnects) with optimized mechanical properties. This provides the required mechanical stability for large-area panels while enabling the increased area needed for zettascale integration.
3Quantity of substance
If interconnect density is increased to achieve higher bandwidth, then manufacturing complexity increases
Solution Approach 1:
Interconnect structures are pre-formed within standardized panel modules before final assembly. Through-panel interconnects and redistribution layers are manufactured as integral parts of the panel using established semiconductor fabrication techniques, reducing on-site manufacturing complexity while achieving high interconnect density.
Solution Approach 2:
The patent introduces intermediate redistribution layers and buffer regions that mediate between high-density local interconnects and lower-density external connections. This allows achieving high interconnect density for bandwidth while managing manufacturing complexity through hierarchical interconnect architecture.
4Reliability
If multiple dies are assembled on a single substrate, then yield issues worsen, but panel-level manufacturing improves reliability
Solution Approach 1:
The system is segmented into multiple independent panels, each containing a manageable number of dies. This allows manufacturing each panel with high yield using wafer-level techniques, then assembling validated panels into the final zettascale system, improving overall reliability while maintaining productivity.
Solution Approach 2:
Individual panels are manufactured and tested as complete functional modules before final system assembly. This preliminary validation ensures each panel meets reliability requirements, improving overall system reliability while maintaining manufacturing yield through modular production and testing.
Data Source
AI summary
Panel-level high performance computing (HPC) computing architectures and methods for making the same are disclosed. Panel architectures with and without glass cores comprise dielectric layers with interconnect structures (vias, conductive traces) to translate die-level pinouts arranged at a fine pitch to panel-level pinouts arranged at a coarser pitch. Local interconnects and local interconnect components provide for electrical communication between integrated circuit dies in a panel. Coreless panel architectures can comprise a glass reinforcement layer to provide additional mechanical stiffness. The glass reinforcement layer can have interconnect structures and a local interconnect component. Panel embodiments with a glass core or glass reinforcement layer can comprise waveguides and channel a liquid coolant therethrough, and can further comprise photonic integrated circuits. Panel-level manufacturing techniques can enable panels having dimensions larger (e.g., greater than 300 mm) than components fabricated using wafer-level manufacturing techniques.