Panel Level MEMS Packaging via Thin-Film Interconnects
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Solution Overview
Problem
Conventional MEMS-on-glass packaging technologies face challenges due to high manufacturing costs, low yield, and bulky package profiles resulting from the thickness of glass substrates, as well as the need for individual fabrication of MEMS and ASIC devices.
Innovation Solution
The approach involves forming a panel of packages with a common connection layer, internal connections for coupling MEMS devices with semiconductor devices, and external connections for interfacing with interconnects, allowing for panel-level packaging that can be individualized later, reducing costs and achieving a low profile without the need for glass substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MEMS-on-glass packaging is used with glass substrates, then device performance is maintained, but package profile becomes bulky and manufacturing cost increases
Solution Approach 1:
The patent extracts and removes the glass substrate from the packaging structure, replacing it with a thin-film connection layer system. This eliminates the bulky glass substrate while maintaining the necessary electrical and mechanical connections between MEMS devices and ASIC devices, thereby reducing package profile without compromising device performance.
Solution Approach 2:
The patent changes the physical parameters of the connection structure by transitioning from thick glass substrates to thin-film connection layers. This parameter change in substrate thickness and material composition enables a low-profile package design while maintaining the required electrical connectivity and mechanical support functions.
2Adaptability or versatility
If individual MEMS and ASIC devices are fabricated separately and then combined, then device integration is achieved, but manufacturing cost increases and yield decreases
Solution Approach 1:
The patent merges the fabrication processes of MEMS devices and ASIC devices into a single integrated panel-level manufacturing process. Multiple devices are fabricated simultaneously on a common substrate using compatible process steps, eliminating the need for separate fabrication and subsequent assembly, thereby reducing manufacturing cost and improving yield.
Solution Approach 2:
The patent creates a universal manufacturing platform that can fabricate multiple types of devices (MEMS and ASIC) using the same process steps and materials. The thin-film connection layer structure serves multiple functions including electrical interconnection, mechanical support, and signal routing, enabling a single manufacturing process to produce integrated device assemblies.
3Reliability
If through-glass-vias and conductive bumps are used for connections, then electrical connectivity is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts and eliminates the complex through-glass-via and conductive bump interconnection structure by replacing it with a planar thin-film connection layer system. This simplifies the manufacturing process by removing multiple high-complexity fabrication steps while maintaining reliable electrical connectivity between devices.
Solution Approach 2:
The patent replaces expensive and complex permanent interconnection structures (through-glass-vias and conductive bumps) with a simpler, thinner, and more cost-effective thin-film connection layer that achieves the same electrical connectivity function with reduced manufacturing complexity.
Data Source
AI summary
Conventional package for integration of MEMS and electronics suffer from profiles that are undesirably high to due to the thickness of the glass. Also in conventional package manufacturing, the MEMS and electronic devices are first individualized, and the individualized MEMS and electronics are combined into a package, and thus can be costly. To address these and other disadvantages, a panel level packaging is proposed. In this proposal, plural MEMS devices are integrated with plural semiconductor devices at a panel level, and the panel is then individualized into separate packages.


