Panel-Level Microelectronic Packaging Without Carrier Debonding
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Solution Overview
Problem
Existing microelectronic device packaging techniques at the panel level are inefficient, leading to high costs, waste, and requiring multiple process steps, often involving steel or glass carriers and complex carrier debonding processes.
Innovation Solution
The use of printed circuit panels that support microelectronic dice with vias for electrical connection, allowing for the formation of redistribution layers and singulation of microelectronic device packages without the need for steel or glass carriers, thereby reducing process complexity and waste.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If steel or glass carriers are used for panel-level packaging, then microelectronic devices can be supported and processed, but process complexity increases due to carrier debonding requirements
Solution Approach 1:
The patent extracts and eliminates the carrier component from the packaging system. Instead of using steel or glass carriers that require debonding processes, the invention uses a molded case that directly receives and secures the panel, removing the intermediate carrier layer and its associated complex processes.
Solution Approach 2:
The patent merges the support function and the packaging function into a single integrated structure. The molded case serves both as the packaging container and as the support structure for the panel, eliminating the need for separate carrier components and simplifying the overall system.
2Reliability
If traditional panel-level packaging is used, then microelectronic devices can be captured in dielectric material, but manufacturing cost increases
Solution Approach 1:
The patent employs a molded case made from cost-effective materials that is designed for single-use packaging applications. The case provides adequate protection and support without requiring expensive reusable carrier systems, reducing overall manufacturing costs while maintaining device encapsulation integrity.
3Ease of operation
If carrier debonding processes are performed, then devices can be released from the panel, but time consumption increases
Solution Approach 1:
The patent removes the debonding step from the process sequence by eliminating the carrier component. Devices are released directly from the panel into the molded case without requiring intermediate debonding operations, significantly reducing process time.
Solution Approach 2:
The molded case is pre-configured with recesses and features that facilitate direct device placement and securing. This preliminary preparation eliminates the need for time-consuming debonding operations, as devices can be directly transferred and secured in their final positions.
4Reliability
If multiple process steps are used for packaging, then devices can be properly assembled, but productivity decreases
Solution Approach 1:
The patent combines multiple packaging functions into a single integrated molded case structure that provides support, protection, and device securing simultaneously. This consolidation reduces the number of sequential process steps required while maintaining assembly quality.
Solution Approach 2:
The molded case is designed to perform multiple functions: supporting the panel, protecting devices during handling, and providing the final packaging structure. This multi-functionality eliminates the need for separate components and processes, thereby increasing productivity.
Data Source
AI summary
Methods may involve supporting a plurality of microelectronic dice on a printed circuit panel. Respective microelectronic dice of the plurality of microelectronic dice may be electrically connected to at least one via of the printed circuit panel. Microelectronic device packages may be singulated from the printed circuit panel, respective microelectronic device packages including at least one microelectronic die of the plurality of microelectronic dice and a portion of the printed circuit panel. Structures may include a plurality of microelectronic dice supported on a printed circuit panel. The printed circuit panel may include vias, subsets of the vias positioned for electrical connection to a respective microelectronic die of the plurality of microelectronic dice.