Panel-Level Multi-Die Packaging With Lithographic VHD Interconnect Vias
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Solution Overview
Problem
Existing panel level packaging technologies for multi-die products face challenges in achieving ultra-fine line spacing (uFLS) for high density die-to-die interconnections, which limits their ability to support Very High Density (VHD) routing.
Innovation Solution
The use of a lithographically defined process to form conductive vias in a foundation layer, enabling the creation of high density routing layers with uFLS for die-to-die interconnections. This process involves a double lithography patterning process, allowing for better alignment and smaller via sizes compared to traditional laser-drilled vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional panel format packaging is used, then manufacturing cost is reduced and productivity is increased, but resolution is limited which prevents ultra-fine line spacing routing
Solution Approach 1:
The patent segments the packaging process into two distinct stages: (1) a panel-level packaging stage that achieves high productivity and cost efficiency, and (2) a subsequent fine-pitch interconnect stage that achieves ultra-fine line spacing. This segmentation allows each stage to optimize for its specific purpose without compromising the other.
Solution Approach 2:
The patent performs preliminary actions by first establishing the panel-level packaging structure with standard routing layers, then subsequently adding the ultra-fine line spacing routing layers. This preliminary action allows the bulk packaging structure to be formed efficiently before applying the high-precision interconnect layer.
2Manufacturing precision
If wafer-based packaging solutions (FO-WLP, eWLB) are used, then high levels of integration are achieved, but manufacturing cost increases and adoption difficulty increases
Solution Approach 1:
The patent applies local quality by implementing ultra-fine line spacing routing only in the specific regions where high-density die-to-die interconnections are required, rather than applying wafer-based packaging techniques across the entire package. This localized application of high-precision routing reduces overall manufacturing cost while maintaining high integration levels where needed.
3Manufacturing precision
If laser-drilled vias are used in panel format packaging, then manufacturing is simplified, but alignment precision and via size are insufficient for VHD routing
Solution Approach 1:
The patent replaces the mechanical laser-drilling process with a lithography-based patterning process for forming vias and routing lines. This substitution enables precise alignment and smaller feature sizes through photolithographic patterning, achieving the required via dimensions and alignment precision for VHD routing that cannot be obtained with laser drilling.
Data Source
AI summary
A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.