Panel-Level Semiconductor Packaging With Shared Seed-Layer Plating
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Solution Overview
Problem
Conventional semiconductor packages face issues of excess cost, decreased reliability, and large package sizes, which hinder efficient manufacturing and performance.
Innovation Solution
The method involves forming electronic devices with a photo-definable and low loss tangent dielectric layer and a seed layer, allowing for the creation of multiple conductive structures, and a manufacturing system that processes subpanels on a carrier panel before singulation, enabling cost reduction, increased reliability, and improved manufacturability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor packaging methods are used, then manufacturing processes are established, but costs are excessive and reliability is decreased
Solution Approach 1:
The patent combines multiple semiconductor components and conductive structures onto a single carrier panel, enabling simultaneous processing and interconnection. This merging approach reduces the number of separate packaging operations required, thereby decreasing manufacturing costs while improving reliability through consistent interconnections formed during panel-level processing.
Solution Approach 2:
The carrier panel serves multiple functions: it acts as a support structure during manufacturing, a platform for forming conductive interconnections, and a temporary substrate for component assembly. This multi-functionality eliminates the need for separate fixtures and processing steps, reducing costs while maintaining high reliability through standardized processes.
2Volume of moving object
If conventional semiconductor packages are used, then devices are produced, but package sizes are too large
Solution Approach 1:
The patent transitions from traditional three-dimensional stacked packaging to a planar two-dimensional arrangement on the carrier panel. Multiple components are distributed across the panel surface with conductive structures forming interconnections in the plane, reducing vertical height and overall package volume while maintaining manufacturing efficiency through panel-level processing.
Solution Approach 2:
The carrier panel is divided into multiple processing zones, with different semiconductor components and conductive structures formed in separate regions. This segmentation allows parallel processing of different component types and interconnection schemes, improving manufacturing efficiency while the overall panel structure maintains compact packaging dimensions.
3Ease of manufacture
If multiple conductive structures are formed individually, then connectivity is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
Multiple conductive structures are formed simultaneously on the carrier panel using a unified deposition and patterning process. The seed layer is deposited across the entire panel, and subsequent electroplating operations create multiple conductive interconnections in parallel, reducing manufacturing complexity and cost compared to forming each structure individually.
Solution Approach 2:
The electroplating process serves multiple functions: it forms conductive interconnections between different component types, creates ground planes, and establishes signal pathways simultaneously. This multi-functional approach simplifies the manufacturing process while managing the complexity of multiple conductive structures through a single integrated process step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach decreases costs, enhances reliability, and improves manufacturability by allowing for efficient formation of conductive structures and signal distribution within semiconductor components, leading to smaller, more reliable electronic devices.
Implementation Method 1
photo-definable and low loss tangent dielectric layer
Implementation Method 2
seed layer from which multiple conductive structures (e.g., conductive pattern(s), conductive stud(s), etc.) are formed
Data Source
AI summary
An electronic device comprises a substrate and a semiconductor component coupled to the substrate. The substrate may include a dielectric layer, a seed layer, a conductive pattern, and an external interconnect first structure coupled to the conductive pattern. The dielectric layer may include photo-definable dielectric material. The conductive pattern and the external interconnect first structure may include one or more electroplated conductive layers formed using the same seed layer of the substrate.