Panel Peripheral Signal Line Layout for Lower Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The dense configuration of signal circuits in high-resolution panel-type electronic devices increases load, affecting performance and reducing quality.
Innovation Solution
The electronic device incorporates a peripheral area with multiple data lines and transistors, where signal lines are arranged in different layers and configurations to reduce parasitic capacitance and optimize signal transmission, including the use of connection portions with branches to share signal lines and increase distance between signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If more electronic elements and signal circuits are installed under the same area to increase resolution, then resolution is improved, but the load of signal circuits increases and performance deteriorates
Solution Approach 1:
The patent applies multi-layer routing to arrange signal lines in different vertical layers (first signal line in first layer, second signal line in second layer). This dimensional separation reduces parasitic capacitance between adjacent signal lines while maintaining high routing density, thus resolving the contradiction between high resolution and signal circuit performance
Solution Approach 2:
The patent segments the signal routing into multiple independent layers, allowing different signal lines to be routed in different layers. This segmentation reduces electromagnetic interference and parasitic capacitance between signals, maintaining performance while supporting high-resolution designs with dense circuit configurations
2Area of stationary object
If signal lines are arranged closer together to increase density, then area utilization is improved, but parasitic capacitance increases and signal transmission quality deteriorates
Solution Approach 1:
By routing signal lines in different vertical layers rather than horizontally adjacent in the same layer, the patent achieves high area utilization while maintaining larger effective spacing between signals through the vertical dimension, thus reducing parasitic capacitance
Solution Approach 2:
The patent introduces intermediate structures (insulation layers, via holes) between signal lines in different layers to further reduce parasitic capacitance. These intermediary elements act as electrical isolators while maintaining compact routing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the load on signal lines, maintains signal transmission efficiency, and supports high-resolution designs while preventing short circuits and excessive parasitic capacitance, thereby enhancing performance and quality.
Implementation Method 1
The first signal line and the second signal line are different layers... reduce parasitic capacitance between adjacent signal lines
Data Source
AI summary
An electronic device, having a peripheral area and including a first data line, a second data line, a first transistor, a second transistor, a first signal line, and a second signal line, is provided. The first data line and the second data line extend along a first direction. The first transistor and the second transistor are adjacently disposed in the peripheral area. The first transistor and the second transistor are respectively electrically connected to the first data line and the second data line. The first signal line and the second signal line extend along the first direction and are at least partially disposed between the first transistor and the second transistor. The first signal line and the second signal line are different layers.