Panel-Scale Transformer Packaging for Reduced Parasitic Inductance
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Solution Overview
Problem
Integrated circuit (IC) transformers face challenges such as increased resistance losses, cumbersome packaging, and limited frequency range, making them less efficient and more costly for miniaturized ICs.
Innovation Solution
The development of a panel-scale packaging apparatus for distributed transformer devices, which involves packaging multiple semiconductor devices on a single large substrate, followed by encapsulation, redistribution layer formation, and singulation, to create a compact and efficient transformer system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging is used for IC transformers, then individual transformer devices can be packaged, but the packaging becomes cumbersome and causes increased parasitics
Solution Approach 1:
The patent merges multiple individual transformer devices onto a single carrier substrate, packaging them together in an array configuration. This consolidation eliminates the need for separate cumbersome packaging for each device and reduces overall parasitic effects by providing a shared, optimized packaging structure with reduced lead lengths and improved electrical connections.
2Ease of manufacture
If IC transformers are made with two windings on the same metal layer or different metal layers, then transformer functionality is achieved, but resistance losses increase compared to discrete components
Solution Approach 1:
The patent changes the geometric parameters of the transformer windings by distributing turns across multiple metal layers with optimized spacing and positioning. This configuration reduces the effective resistance by minimizing current path length and optimizing the conductor geometry, thereby reducing I²R losses while maintaining the integrated manufacturing approach.
3Productivity
If multiple die are disposed with predetermined pitch on carrier member, then fill factor of 70 percent and greater is achieved, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the transformer device into multiple discrete die that are disposed in an array on a carrier substrate. Each die can be manufactured independently with standard precision requirements, and the high fill factor is achieved through the systematic arrangement and dense packing of these segmented units, distributing the precision requirements across multiple identical components rather than requiring one large complex device.
Data Source
AI summary
A panel scale packaging apparatus of a plurality of transformer devices. The apparatus has a plurality of die comprising a plurality of transformer devices spatially disposed in a predetermined pattern formed on a portion of the carrier member that has been released to achieve a fill factor of 70 percent and greater overlying the front side surface such that each pair of die are configured with a predetermined pitch between the pair of die. The apparatus has an encapsulating material overlying a surface region of the plurality of die that fills each of the regions defining the pitch to form an upper surface region of encapsulating material overlying an entirety of the plurality of die to seal each die bounded by a portion of the encapsulating material.