Para-Phase Clocking for Skew Control in SoC Design
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Solution Overview
Problem
In large synchronous systems, achieving strict global synchrony is challenging due to increasing complexity and power consumption in clock distribution, leading to issues like clock skew and hold-time violations, especially in billion transistor system-on-chip designs, where modularized designs and mesochronous clocking are sought to avoid these problems.
Innovation Solution
The proposed method, Para-Phase Clocking (PPC), employs a mesochronous clocking scheme with a directed skew in two dimensions, ensuring timing-safe data transfer by synchronizing clock edges and using acknowledging signals to prevent signal loss, allowing for robust and scalable clock distribution with reduced power consumption and avoiding metastability issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If strict global synchrony is implemented in large synchronous systems, then timing precision is improved, but device complexity and power consumption increase significantly
Solution Approach 1:
The patent divides the chip into multiple clock phase regions, each with its own local clock phase, rather than using a single global clock phase. This segmentation allows independent timing control in different regions, reducing the complexity of global clock distribution while maintaining timing precision within each region.
Solution Approach 2:
The patent implements local clock phase optimization by allowing different clock phases in different spatial regions of the chip. Each region can be independently tuned to optimize timing for local circuits, reducing the need for complex global skew control while improving local timing precision.
2Measurement precision
If distributed active skew control is used to minimize clock skew, then timing precision is improved, but power consumption increases by more than 30%
Solution Approach 1:
The patent segments the clock distribution into multiple independent phase regions, eliminating the need for continuous active skew control across the entire chip. Each region operates independently with fixed phase relationships, dramatically reducing power consumption while maintaining adequate skew control for local operations.
Solution Approach 2:
The patent changes the clock distribution parameter from a single globally-controlled phase to multiple independently-defined phases across different regions. This parameter change allows static phase relationships to replace dynamic active skew control, reducing power consumption by eliminating continuous adjustment mechanisms.
3Speed
If standing waves are used for clock distribution, then clock frequency and speed are improved, but the clock frequency becomes dependent on component parameters
Solution Approach 1:
The patent segments the clock distribution into multiple independent phase regions that can operate at different frequencies and phases. This segmentation eliminates the need for standing wave patterns that require precise frequency matching, allowing each region to be independently optimized without component parameter dependencies.
4Device complexity
If larger clock skew is accepted to simplify design, then device complexity is reduced, but performance deteriorates due to increased timing margin requirements
Solution Approach 1:
The patent applies local quality optimization by allowing different clock phases in different spatial regions. This enables the system to maintain small timing margins locally (high performance) while using fixed phase relationships rather than active control (low complexity), achieving both goals simultaneously.
Data Source
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AI summary
A method of providing or transporting a timing signal between a number of circuits, electrical or optical, where each circuit is fed by a node. The nodes forward timing signals between each other, and at least one node is adapted to not transmit a timing signal before having received a timing signal from at least two nodes. In this manner, the direction of the timing skew between nodes and circuits is known and data transport between the circuits made easier.