Paraelectric Adder Reset Mechanism for Compact Low-Power Multipliers
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Solution Overview
Problem
Conventional multiplier cells in CMOS logic require numerous transistors, leading to increased power consumption and area, which poses challenges in achieving lower power consumption and compact design, especially in battery-powered devices.
Innovation Solution
The use of non-linear polar materials such as ferroelectric or paraelectric materials in majority and minority gates within the multiplier cell, combined with a transmission-gate based reset mechanism, reduces the number of transistors and interconnects, enabling lower power consumption and more compact designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional CMOS logic gates (AND, OR, XOR) are used to build a 1-bit full adder and multiplier cell, then the circuit can perform basic arithmetic operations, but the number of transistors increases, leading to increased power consumption and area
Solution Approach 1:
The patent changes the fundamental operating parameter of the logic gates from conventional CMOS switching thresholds to threshold voltages determined by capacitor voltage divisions. By using capacitors with specific voltage ratios (e.g., 1:2, 1:3) connected to threshold gates, the circuit achieves logic functionality with fewer transistors. The threshold gate's switching threshold is set by the voltage division ratio of the capacitors, allowing compact implementation of AND, OR, and full adder functions.
Solution Approach 2:
The patent employs a composite structure combining capacitors with threshold gates to create logic gates with reduced transistor count. The capacitor-threshold gate combination replaces multiple CMOS transistors, where the capacitor network provides both the threshold setting and the logic function implementation, achieving area and power reduction while maintaining computational capability.
2Power
If the number of transistors is reduced to lower power consumption, then power efficiency improves, but circuit area and design complexity may be affected
Solution Approach 1:
The patent merges the threshold-setting function and the logic operation function into a single integrated structure. The capacitors that would traditionally be separate components for threshold adjustment are combined with the threshold gate to form a unified logic element. This merging eliminates the need for separate transistor networks for threshold control and logic operation, significantly reducing the overall circuit area while maintaining low power consumption.
Solution Approach 2:
The threshold gate structure with capacitor voltage division serves multiple functions simultaneously: it provides logic operation (AND, OR, NOR), sets switching thresholds, and enables compact circuit implementation. This multi-functionality allows the same structural motif to be reused across different logic operations, reducing both area and transistor count compared to dedicated CMOS implementations of each gate type.
3Adaptability or versatility
If conventional logic gates are used, then the circuit can operate continuously, but it cannot achieve intermittent operation capabilities for ultra-low power modes
Solution Approach 1:
The patent enables periodic or intermittent operation by allowing the capacitor voltage divisions to be reset or reconfigured between computation cycles. The threshold gates can be held in a stable state with minimal power consumption, and computation can be activated periodically by updating the capacitor voltages or input signals. This periodic action capability allows the circuit to switch between active computation and ultra-low power standby modes.
Solution Approach 2:
The capacitor voltage divisions are pre-configured to establish the threshold gate switching thresholds before computation begins. This preliminary setup allows the circuit to remain in a low-power state with pre-set thresholds, and computation can be rapidly activated by simply applying input signals without requiring continuous power for threshold maintenance. The preliminary capacitor charging establishes the operational parameters in advance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a significant reduction in power consumption and area, allowing for extremely compact multiplier circuitry with intermittent operation capabilities and reduced voltage requirements, while maintaining performance.
Implementation Method 1
a first non-linear input capacitor including a paraelectric material
Data Source
AI summary
A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and/or minority gates. The majority and/or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and/or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and/or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.