Parallel Accumulator DQ Training for Flash Storage Timing Alignment
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Solution Overview
Problem
Flash storage devices face data output errors due to misalignment of DQ pins with respect to the data strobe (DQS) timing, leading to increased uncorrectable errors and performance degradation, especially at higher speeds, which is inefficiently addressed by serial read training methods that are time-consuming and costly.
Innovation Solution
A parallel approach using a plurality of accumulators to simultaneously compare data output with a test pattern, identifying mismatches and adjusting DQS-DQ timings to align DQ pins with the DQS, thereby reducing read errors and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If serial read training methods are used to align DQ pins with DQS timing, then data integrity can be improved, but training time and cost increase significantly
Solution Approach 1:
The patent segments the read training process into parallel operations by using multiple accumulators that simultaneously compare different DQ lines against the test pattern. Instead of training each DQ line sequentially, the system divides the training workload across multiple parallel comparison units, each handling a specific DQ line independently but concurrently.
Solution Approach 2:
The patent introduces a temporal dimension to the training process by performing multiple comparisons simultaneously at different time points. The controller compares DQ lines at different offsets relative to the data strobe in parallel, transforming a sequential time-consuming process into a parallel space-time efficient process.
2Productivity
If higher data transfer speeds are implemented, then productivity increases, but misalignment errors between DQ pins and DQS timing increase
Solution Approach 1:
The patent performs preliminary alignment training before normal data operations begin. By conducting read training at lower speeds first to establish correct DQ-DQS timing relationships, and only transitioning to higher speeds after proper alignment is achieved, the system prevents timing misalignment errors from occurring during high-speed operation.
Solution Approach 2:
The patent implements feedback mechanisms where the controller monitors mismatch counts from the parallel comparisons and uses this information to adjust timing parameters. When mismatches are detected at lower speeds, the controller modifies DQ timing offsets and re-tests until optimal alignment is achieved, ensuring reliable operation before high-speed data transfer begins.
3Productivity
If parallel accumulator method is used for read training, then training time is reduced, but device complexity increases
Solution Approach 1:
The patent designs the accumulator structure to serve multiple functions: comparing data bits, counting mismatches, and providing feedback for timing adjustment. By making the accumulators multi-functional rather than dedicated to single purposes, the system reduces overall device complexity while maintaining parallel training efficiency.
Data Source
AI summary
Aspects of a storage device including a controller memory, a die memory, and a plurality of accumulators corresponding to individual DQs are provided for accelerated DQ training and error detection. A controller stores first data in the controller memory, transfers second data to the die memory over an n-bit bus, and receives n bits of the second data from the die memory based on a DQS. The controller then compares n bits of the first data with n bits of the second data to produce n bit results received into respective accumulators, and the controller simultaneously updates different accumulators in response to bit mismatches. During DQ training, if an accumulator value meets a mismatch threshold, the controller modifies a DQS-DQ timing accordingly. During error detection of a read scrambled page, if an accumulator value does not meet an entropy threshold, the controller identifies an error associated with the page.