Parallel ACS Circuit for Low-Latency Viterbi Decoding
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Solution Overview
Problem
The Viterbi decoder's Add-Compare-Select (ACS) unit experiences high processing latency and complexity due to its sequential nature, which limits decoding speed and increases chip area and power consumption, especially as code complexity increases.
Innovation Solution
The implementation of a parallel comparison mechanism using additional first-level comparators and a logic module for Boolean operations to generate select control signals, reducing the need for upper-level comparison-multiplexing and simplifying the circuit design, thereby reducing latency and gate count in the ACS unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a sequential compare-select algorithm is used in the ACS unit, then the circuit design is simple, but the processing latency is long and decoding speed is limited
Solution Approach 1:
The patent segments the comparison task into multiple hierarchical levels. Instead of sequentially comparing all pairs, the ACS unit divides the set of path metrics into groups and performs comparisons at different levels simultaneously. First-level comparators handle initial comparisons, then second-level comparators process the results in parallel, effectively reducing the critical path delay while maintaining systematic circuit organization.
Solution Approach 2:
The patent transforms the one-dimensional sequential comparison process into a multi-dimensional hierarchical structure. By organizing comparators in multiple levels and allowing simultaneous operations across different levels, the system adds a temporal dimension to the comparison process, enabling parallel execution and reducing overall latency without exponentially increasing complexity.
2Reliability
If the code complexity increases, then the decoding capability improves, but the ACS unit occupies greater chip area and consumes more power
Solution Approach 1:
The patent segments the ACS unit into modular hierarchical levels, where each level handles a specific subset of comparisons. This modular structure allows the circuit to scale with code complexity in a controlled manner, adding only the necessary number of comparators at each level rather than requiring a complete redesign for higher complexity codes.
Solution Approach 2:
The patent implements a comparison structure that performs slightly more comparisons than the absolute minimum required, using additional first-level comparators that feed into a shared second-level comparison network. This approach provides redundancy that simplifies the overall control logic and enables parallel processing, achieving better area-time tradeoff for handling increased code complexity.
3Reliability
If the code complexity increases, then the decoding capability improves, but the processing speed decreases due to increased computational intensity
Solution Approach 1:
The patent divides the computationally intensive ACS task into multiple parallel comparison stages. By segmenting the work across hierarchical levels with simultaneous operations, the system maintains high decoding speed even as code complexity increases, since each segment processes a subset of data in parallel rather than sequentially.
Solution Approach 2:
The patent ensures continuous processing by organizing the hierarchical comparator structure so that while first-level comparators are processing one set of inputs, second-level comparators are simultaneously processing results from previous cycles. This overlapping and continuous operation eliminates idle time and maintains high productivity regardless of code complexity.
Data Source
AI summary
System and method of comparing-selecting state metric values for high speed Viterbi decoding. In an Add-Compare-Select (ACS) unit, a select control signal is produced by Boolean operations on comparator decision signals and used to control a multiplexer structure. The comparator decision signals can be generated in parallel by an array of comparators comparing all possible pairs of a set of state metrics values. The Boolean operations are predefined through Boolean algebra that uses the decision signals as variables and complies with restriction imposed by the selection criteria, e.g., to select an minimum or maximum value of the set of state metrics values. The Boolean operations are performed by a logic module implemented using basic logic gates, such as AND, OR and NOT. As a result, the multiplexer structure that receives the set of input values can output the optimum value responsive to the select control signal.