Parallel ADC Charge Redistribution Without Output Buffering
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Solution Overview
Problem
High-speed, high-resolution analog to digital converters (ADCs) require complex and power-intensive output buffers to distribute sampled voltage across multiple parallel channels, leading to design challenges and increased power consumption.
Innovation Solution
Analog to digital converting system utilizing a charge redistribution sampler with a conductive interconnect wiring pattern and a sample and hold circuit devoid of an output buffer, where the hold capacitance is formed by a combination of a distinct hold capacitor and distributed parasitic capacitance, allowing charge redistribution among multiple ADCs without the need for a high-speed output buffer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-speed output buffer is used to distribute sampled voltage across multiple parallel channels, then the sampling rate and resolution are improved, but the power consumption and device complexity increase significantly
Solution Approach 1:
The patent extracts and eliminates the output buffer from the sample and hold circuit by implementing a charge redistribution architecture. The hold capacitance directly drives the capacitive digital-to-analog converters of multiple parallel ADCs through conductive interconnect wiring, removing the need for a separate high-speed output buffer stage that consumed significant power.
Solution Approach 2:
The hold capacitance serves multiple functions simultaneously: it holds the sampled voltage and directly provides charge to all parallel ADC channels through the conductive interconnect. The capacitive DACs of the parallel ADCs themselves serve as the distribution mechanism, eliminating the need for an external buffer service.
2Speed
If a high-speed output buffer is used to distribute sampled voltage, then the sampling rate is improved, but the design complexity increases
Solution Approach 1:
The output buffer stage is extracted and removed from the system. The sample and hold circuit's hold capacitance directly interfaces with the parallel ADCs through simple conductive interconnect wiring, eliminating the complex buffer design requirements.
Solution Approach 2:
The function of the output buffer is merged into the conductive interconnect wiring pattern that naturally distributes the sampled voltage to all parallel ADC channels. The interconnect wiring serves both as signal distribution path and as part of the overall capacitance model, simplifying the architecture.
3Measurement precision
If parasitic capacitance of conductive interconnect wiring is minimized, then signal integrity is improved, but the hold capacitance value decreases requiring larger distinct hold capacitor
Solution Approach 1:
The patent converts the harmful parasitic capacitance of the conductive interconnect wiring into a beneficial component by including it as part of the total hold capacitance. The distributed parasitic capacitance along with the distinct hold capacitor forms the complete hold capacitance that drives the parallel ADCs, turning a previously problematic element into a useful resource.
4Productivity
If parallel ADC architecture is used to achieve high sampling rates, then the productivity is improved, but the gain matching between channels becomes more difficult
Solution Approach 1:
The sample and hold circuit is merged with the input stage of all parallel ADCs through the common hold capacitance and conductive interconnect. This ensures that all ADC channels receive the exact same sampled voltage signal simultaneously, guaranteeing identical gain characteristics across all channels without requiring additional matching adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption, simplifies design, and enables faster sampling rates with improved gain matching and reduced thermal noise, eliminating the need for complex output buffering and minimizing the impact of parasitic capacitance.
Implementation Method 1
a hold capacitance formed by a parallel combination of a distinct hold capacitor and the distributed parasitic capacitance of the conductive interconnect wiring pattern
Implementation Method 2
During each hold phase of the sample and hold circuit, the charge on the hold capacitance is transferred to the capacitors of a capacitor digital to analog converter of a successive one of the plurality of analog to digital converters
Implementation Method 3
a conductive interconnect wiring pattern connecting inputs of the plurality of analog to digital converters in parallel
Data Source
AI summary
An analog to digital converting system (200) includes an analog to digital converter (ADC) circuit that is formed by a plurality of parallel ADCs (ADC 1 ADC N) for continuous sequential processing of an input analog voltage signal. Each of the ADCs is a type that employs a capacitor digital to analog converter (DAC) (209, 701) therein. The system further includes a sample and hold circuit (220) coupled to the parallel ADCs by a conductive interconnect wiring pattern (203). The sample and hold circuit includes a sampling switch (207) and a hold capacitance formed by the parallel combination of a hold capacitor (205) and the distributed parasitic capacitance (204) of the conductive interconnect wiring pattern (203). During the hold phase of the sample and hold circuit, charge is redistributed from the hold capacitance to all of the capacitors (211) of the capacitor DAC, which serve as a secondary hold capacitance.