Parallel ADC Clock Skew Correction for Accurate Digital Outputs
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Solution Overview
Problem
Clock skews between analog-to-digital converters (ADCs) operating in parallel lead to differences in digital output values due to signal delays in circuit traces, affecting the accuracy of high-speed ADC systems.
Innovation Solution
A system that adjusts the skew between clock signals received by two ADCs using a correction signal generated from their digital output signals, employing a correction estimator and a timing or skew adjuster to synchronize the clock signals, ensuring they have the same period and duty cycle as a master clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple ADCs operate in parallel with different clock signal paths, then the sampling rate and conversion capability are improved, but clock skew between ADCs causes differences in digital output values
Solution Approach 1:
The patent implements a feedback mechanism where the digital output signals from multiple ADCs are compared, and the difference signals are used to adjust the clock signal timing. Specifically, the system generates difference signals by comparing digital outputs from first and second ADCs, then uses these difference signals to adjust the second clock signal's timing relative to the first clock signal, creating a closed-loop feedback system that continuously corrects skew-induced errors.
Solution Approach 2:
The patent dynamically changes the timing parameter of the clock signal to compensate for skew. The system adjusts the phase or delay of the second clock signal based on the detected output differences between ADCs. This parameter adjustment is achieved through timing adjustment circuits that modify the clock signal characteristics in real-time based on feedback from the ADC output comparison.
2Ease of operation
If clock signal traces are lengthened to reach all ADCs, then signal distribution is improved, but signal delay differences increase causing greater skew
Solution Approach 1:
The patent transforms the static clock distribution network into a dynamic system where clock signal timing can be adjusted. Instead of using fixed trace lengths, the system employs adjustable timing circuits that can dynamically modify the delay characteristics of clock signals delivered to different ADCs, allowing the system to adapt to and compensate for path length differences.
Solution Approach 2:
The patent applies preliminary timing adjustment to clock signals before they reach the ADCs. The system pre-compensates for expected skew by adjusting the clock signal timing in advance based on known or measured path differences, ensuring that all ADCs receive properly synchronized clock edges despite varying trace lengths.
3Productivity
If ADC elements are interleaved to increase sampling rate, then conversion speed is improved, but timing synchronization becomes more difficult
Solution Approach 1:
The patent uses feedback to continuously monitor and correct timing differences between interleaved ADC elements. By comparing the digital outputs from interleaved converters and feeding back the difference information to timing adjustment circuits, the system maintains synchronization even as multiple ADC elements operate at high speeds with potentially different path delays.
Data Source
AI summary
Skew between a first clock signal received by a first analog-to-digital converter (ADC) and a second clock signal received by a second ADC is adjusted to minimize error. Each ADC has an ADC element that produces a respective first or second digital output signal in response to an analog input signal and a respective first or second clock signal. A correction signal is produced in response to the first and second digital output signals. The skew between the first and second clock signals is then adjusted in response to the correction signal.