Parallel Noise-Shaping ADC Architecture for Wideband Resolution
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Solution Overview
Problem
Conventional analog-to-digital converters (ADCs) face limitations in achieving high instantaneous bandwidth and resolution, particularly at very high sample rates, due to issues such as quantization noise, clock jitter, and thermal noise, which restrict their performance in modern electronic applications.
Innovation Solution
The implementation of a Multi-Channel Bandpass Oversampling (MBO) technique that uses continuous-time Diplexed Feedback Loops for quantization noise shaping and Moving Average Reconstruction filters to minimize phase and amplitude distortion, allowing for higher resolution and bandwidth, and active calibration to reduce component tolerance effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional flash converters are used to achieve very high instantaneous bandwidth, then bandwidth is improved, but resolution is limited by practical implementation impairments such as clock jitter, thermal noise, and rounding/gain inaccuracies
Solution Approach 1:
The converter is divided into multiple parallel sub-converters (e.g., 4 sub-converters), each processing a portion of the input signal. Each sub-converter operates at a lower individual bandwidth but collectively they achieve the desired total bandwidth through parallel processing, while each sub-converter can maintain higher resolution
Solution Approach 2:
Multiple low-resolution outputs from parallel sub-converters are combined through digital signal processing to produce a high-resolution output. The digital combination process integrates the results from all sub-converters to achieve the desired effective resolution (e.g., 10-12 bits) while maintaining high instantaneous bandwidth
2Measurement precision
If conventional pipeline converters are used to achieve better precision, then resolution is improved, but instantaneous bandwidth is limited to less than about 1 GHz
Solution Approach 1:
The conversion process is segmented into multiple parallel pipeline stages, where each stage processes a different portion of the signal spectrum. This allows the overall system to achieve high resolution through the combined output of multiple stages while each individual stage can operate at lower bandwidth requirements
Solution Approach 2:
The patent transitions from a single-dimensional time-domain processing approach to a multi-dimensional approach by introducing parallel processing channels. This dimensional expansion allows simultaneous achievement of high resolution (through multiple processing paths) and high bandwidth (through parallel operation)
3Measurement precision
If oversampling converters are used to reduce quantization noise, then resolution is improved, but the raw high-speed converters must operate at very high sample rates with only low-resolution capability
Solution Approach 1:
The patent implements feedback mechanisms where the output of each sub-converter is fed back and combined with other sub-converter outputs through digital signal processing. This feedback and combination process allows the system to achieve high effective resolution by correcting and refining the low-resolution individual outputs
Solution Approach 2:
The system dynamically adjusts operating parameters of the parallel sub-converters, including sampling rates and filtering characteristics, to optimize the balance between resolution and bandwidth. By changing these parameters adaptively, the system achieves high resolution without requiring excessively high sample rates from individual converters
Data Source
AI summary
Provided are, among other things, systems, methods and techniques for converting a continuous-time, continuously variable signal into a sampled and quantized signal. According to one representative embodiment, an apparatus includes multiple quantization-noise-shaping continuous-time filters, each in a separate processing branch and having an adder that includes multiple inputs and an output; an input signal is coupled to one of the inputs of the adder; the output of the adder is coupled to one of the inputs of the adder through a first filter; and the output of a sampling/quantization circuit in the same processing branch is coupled to one of the inputs of the adder through a second filter, with the second filter having a different transfer function than the first filter.