Parallel ADC Sub-Channel Compensation for Offset and Skew

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Solution Overview

Problem

Existing data communication systems face challenges in achieving high data processing and exchange rates due to limitations in analog to digital converter (ADC) speed and performance, leading to issues like DC offset, gain offset, and skew when distributing high data rate signals into multiple sub-channels for distributed processing.

Innovation Solution

A method and apparatus utilizing a time-interleaving analog to digital conversion system with multiple ADCs, DC offset compensation, and sub-channel gain mismatch compensation to process analog signals into digital signals, ensuring accurate re-assembly by removing inconsistencies and mismatches across sub-channels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the A/D converter operates at higher rates to accommodate increased data processing speeds, then the data exchange rate is improved, but the performance deteriorates due to limitations in ADC speed and track and hold operation

Engineering Contradiction:
Improvedata exchange rateVSAvoidADC performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent divides a single high-speed A/D conversion task into multiple parallel lower-speed conversions using multiple ADCs. Each ADC converts a portion of the analog signal at a manageable rate, and the digital outputs are combined through time-interleaving to reconstruct the high-rate digital signal. This segmentation allows the system to achieve high data exchange rates without requiring individual ADCs to operate beyond their performance capabilities.

Inventive Principle:
Principle #1Segmentation

2Productivity

If the high data rate signal is split into multiple sub-channels for distributed processing, then the processing rate per channel is reduced, but processing variations occur across sub-channels causing DC offset, gain offset, and skew

Engineering Contradiction:
Improveprocessing rate per channelVSAvoidsignal consistency across sub-channels
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent incorporates feedback mechanisms where the digital outputs from multiple ADCs are monitored and compared. DC offset compensation circuits measure and eliminate bias differences between sub-channels, while gain mismatch compensation adjusts amplitude variations. Skew compensation aligns timing differences by detecting and correcting phase shifts. These feedback-based compensation techniques ensure that distributed processing across multiple sub-channels maintains signal consistency and accuracy.

Inventive Principle:
Principle #23Feedback

3Productivity

If multiple ADCs are used in parallel to achieve high data rates, then the data processing capability is improved, but device complexity increases due to multiple converters and compensation circuits

Engineering Contradiction:
Improvedata processing capabilityVSAvoidnumber of ADCs and compensation circuits
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent designs the multiple ADCs and associated compensation circuits to perform multiple functions. The same parallel ADC structure handles both high-rate conversion and provides redundancy for error correction. Compensation circuits serve dual purposes of offset correction and gain normalization. The time-interleaving multiplexer efficiently switches between multiple ADC outputs, combining functions of sampling, switching, and signal reconstruction in a single integrated approach, thereby reducing overall system complexity despite using multiple components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7808407B2Sub-channel distortion mitigation in parallel digital systems
Publication Date: 2010.10.05 MARVELL ASIA PTE LTD
  • US7808407B2 patent drawing
  • US7808407B2 patent drawing
  • US7808407B2 patent drawing

AI summary

A method and apparatus for compensating for gain offset, bias offset, and skew in a parallel processing environment is disclosed. The method and apparatus may be configured to compensate for mismatches between the sub-channel signals in a parallel ADC. This allows for accurate combination of the signals on the sub-channels. The method and apparatus may be utilized in a high speed data communication system having two or more channels, each of which are interleaved into two or more sub-channels. In one embodiment a DC loop processes signals on two or more sub-channels to account for and remove unwanted bias offset. In one embodiment a sub-channel gain mismatch compensation system (SCGMC) processes signals on two or more sub-channels to account for and remove unwanted gain offset. In one embodiment a skew compensation system, such as a parallel interpolator, processes signals on two or more sub-channels to remove unwanted skew across sub-channels.