Parallel Adder Tree for Prime Number Division in Memory Interleaving
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Solution Overview
Problem
Existing methods for performing integer division, particularly in the context of Compute Express Link (CXL) technology, are time-consuming and resource-intensive due to their iterative nature, leading to performance bottlenecks in applications like memory interleaving.
Innovation Solution
A hardware-based integer divide-by-prime operation is implemented using a tree of parallel adders, allowing for a single clock cycle division. This approach involves determining a tree of parallel adders based on the input values, including the number of bits in the input value and the divisor, and using this tree to obtain an output value for calculating physical addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If iterative division methods are used for memory interleaving, then the division can be performed with simple logic, but the operation time increases and performance decreases
Solution Approach 1:
The patent segments the division operation into multiple parallel stages, where each stage processes a portion of the division simultaneously. This is achieved by dividing the input address into segments and using multiple adders to process different segments in parallel, reducing the total time required while maintaining accuracy.
Solution Approach 2:
The patent transitions from a sequential single-cycle division approach to a multi-stage parallel processing architecture. By adding the dimension of parallel stages with logarithmic depth, the system achieves both reduced time complexity and acceptable logic resource usage, resolving the contradiction between speed and complexity.
2Productivity
If parallel adder trees are used for single-cycle division, then the division speed increases, but the logic resources and device complexity increase
Solution Approach 1:
The patent employs a dynamic approach where the number and configuration of parallel adders are adjusted based on the specific division requirements. The architecture can adaptively select the appropriate number of parallel stages and adders needed, optimizing the balance between speed and resource usage for different operating conditions.
Solution Approach 2:
The patent changes key parameters of the division architecture, such as the number of parallel stages, the depth of the adder tree, and the allocation of logic resources, to optimize performance. By adjusting these parameters based on the specific application requirements, the system achieves high-speed division while controlling logic resource consumption.
3Reliability
If prime number divisors are used for memory interleaving, then the address distribution improves, but the division operation becomes more time-consuming
Solution Approach 1:
The patent performs preliminary preparation by pre-computing and storing divisor-specific parameters and lookup tables for prime number divisors. This allows the actual division operation to be executed quickly by simply retrieving and applying pre-computed values, maintaining the benefits of prime number interleaving while minimizing calculation time.
Solution Approach 2:
The patent introduces intermediary structures such as lookup tables and pre-computed parameter sets that act as mediators between the input address and the final divided result. These intermediaries enable fast division by prime numbers without requiring complex real-time calculations, thus preserving address distribution quality while reducing time loss.
Data Source
AI summary
A processing unit, associated with a host device, adapted to receive a request to calculate a first physical address of an external device based on a second physical address of the host device; determine a tree of parallel adders corresponding to the division operation; obtain an output value from the tree of parallel adders based on the input values; and calculate the first physical address using the output value. The first physical address of the external device is to be calculated based on a division operation that divides the second physical address by a divisor. The tree of parallel adders is determined based on input values that include a number of bits of the second physical address and a divisor.