Parallel Address Generation Units for Superscalar Throughput
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Solution Overview
Problem
Current software development for parallel execution on multiprocessor systems faces challenges in efficiently describing the system's behavior and interactivity, leading to inefficiencies in programming and execution, particularly due to the need for complex hardware-specific optimizations and rewrites for different hardware platforms.
Innovation Solution
A method and system that allow users to specify multiple views of a system's operation, including memory, communication, and processing aspects, which are then used by a compiler to generate executable code optimized for efficient parallel execution on multiprocessor systems, using a programming model that supports adaptable communications and memory structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple parallel address generation units are used to support advanced addressing modes in superscalar processors, then instruction execution capability and parallelism are improved, but hardware complexity and area requirements increase
Solution Approach 1:
The address generation system is divided into multiple independent address generation units (AGUs), each capable of handling specific addressing modes. This segmentation allows parallel address computation for multiple instructions simultaneously, improving instruction execution capability while keeping each individual AGU relatively simple in structure.
Solution Approach 2:
Each address generation unit is designed with multi-functionality to handle various addressing modes (auto-increment, pre-decrement, post-decrement, register indirect, immediate, etc.). This universality reduces the need for separate dedicated hardware for each addressing mode, thereby controlling hardware complexity while supporting diverse instruction types.
2Adaptability or versatility
If multiple address generation units with support for advanced addressing modes are implemented, then software portability across different processor architectures is improved, but hardware area requirements increase
Solution Approach 1:
The processor implements a comprehensive set of addressing modes through multiple AGUs that can handle various addressing techniques (auto-increment, pre-decrement, post-decrement, register indirect, immediate, relative, etc.). This universal support allows software written for one architecture to be more easily ported to others, improving software portability while the modular design helps control the hardware area footprint.
Solution Approach 2:
The address generation units are designed to be dynamically configurable through control signals that select different addressing modes based on the instruction being executed. This dynamic operation allows the same hardware structure to adapt to different addressing requirements, reducing the need for dedicated hardware for each mode and thereby controlling area requirements.
3Productivity
If superscalar architecture with multiple instruction streams is used, then processing throughput is improved, but control logic complexity and power consumption increase
Solution Approach 1:
The processor architecture is segmented into multiple independent instruction streams with separate fetch, decode, and execution paths. Multiple address generation units are allocated to different instruction streams, allowing parallel processing of multiple instructions simultaneously. This segmentation improves processing throughput while distributing control logic across multiple simpler units rather than one complex centralized controller.
Data Source
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AI summary
Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. A first address generator unit may be configured to perform an arithmetic operation dependent upon a first field of the plurality of fields. A second address generator unit may be configured to generate at least one address of a plurality of addresses, wherein each address is dependent upon a respective field of the plurality of fields. A parallel assembly language may be used to control the plurality of address generator units and the plurality of pipelined datapaths.