Parallel AES Rijndael Processing for Smart Card Throughput
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Solution Overview
Problem
Conventional Rijndael algorithm implementation apparatuses in resource-constrained environments, such as smart cards, face reduced throughput due to the need for a single data processing module to perform all rounds sequentially, leading to decreased processing speed and increased resource requirements.
Innovation Solution
The apparatus and method implement the AES Rijndael algorithm through parallel-processing AES rounds using multiple input data handling routines, with a round key generator, initial round key adder, operators for byte substitution, column mixing, and round key addition, and a register part for temporary storage, allowing simultaneous data input and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single data processing module is used to perform all AES rounds sequentially, then device complexity is reduced, but processing speed and throughput deteriorate
Solution Approach 1:
The patent divides the AES processing into multiple parallel data processing modules (first data processing module, second data processing module, etc.), where each module handles a portion of the rounds. This segmentation enables parallel execution of multiple AES rounds simultaneously, thereby increasing throughput while maintaining manageable complexity in each individual module.
Solution Approach 2:
The patent transitions from sequential processing (one dimension in time) to parallel processing by introducing multiple data processing modules operating simultaneously. This dimensional change from temporal sequencing to spatial parallelism allows multiple rounds to be processed at the same time, dramatically improving processing speed without proportionally increasing device complexity.
2Productivity
If multiple data processing modules are used for parallel AES rounds, then processing speed is improved, but resource requirements increase
Solution Approach 1:
The patent merges multiple data processing modules into a unified parallel processing architecture where modules share common resources such as the round key generator, S-box substitution tables, and output combining logic. This merging approach allows the system to achieve high throughput through parallelism while reducing the total resource footprint compared to completely independent modules.
Solution Approach 2:
Each data processing module is designed with universal functionality to handle multiple operations (byte substitution, shift row, mix column, add round key) within a single modular structure. This multi-functionality reduces the need for separate dedicated hardware for each operation, thereby decreasing overall resource requirements while maintaining high processing capability.
3Quantity of substance
If data is processed sequentially through all rounds, then resource requirements are reduced, but processing time increases
Solution Approach 1:
The patent implements preliminary action by pre-generating round keys using the key expansion algorithm before the actual AES rounds are executed. The round key generator produces all necessary round keys in advance, allowing the parallel data processing modules to immediately begin processing without waiting for key generation during runtime, thereby reducing processing time without significantly increasing resource usage.
Data Source
AI summary
An encryption and decryption apparatus includes a round key generator generating at least one round key for iterative operations in each of a plurality of rounds using an input key for one of the encryption and decryption; an initial round key adder receiving a plurality of divided parts of an input data, consecutively receiving a plurality of parts of an initial round key which is output from the round key generator for an initial round and corresponds to each of the divided input data, and adding the input data and the corresponding part of the initial round key; a first operator receiving a first data which is output from the initial round key adder and a part of the round key which is output from the round key generator and performing operations for one of the encryption and decryption; a second operator receiving a second data which is output from the initial round key adder and another part of the round key which is output from the round key generator, and performing operations for one of the encryption and decryption; and a register part temporarily storing the first data which is output from the first operator and the second data which is output from the second operator, inputting the first and second data to the first and second operators, respectively, for operations of a next round among the plurality of the rounds, and outputting an encrypted or decrypted data when the plurality of the rounds are completed.